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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN"
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<title>SystemVerilog Cheatsheet</title>
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<div id="content" class="content">
<h1 class="title">SystemVerilog Cheatsheet</h1>
<div id="table-of-contents" role="doc-toc">
<h2>Table of Contents</h2>
<div id="text-table-of-contents" role="doc-toc">
<ul>
<li><a href="#orgb5f89d6">1. Compile/Run</a>
<ul>
<li><a href="#org0ed20bb">1.1. TL;DR</a></li>
<li><a href="#org40a7bca">1.2. Detailed Explanation:</a></li>
</ul>
</li>
<li><a href="#org8c4e125">2. Modules</a>
<ul>
<li><a href="#org43e5310">2.1. Defining a module</a></li>
<li><a href="#orgf7da603">2.2. Creating module instances (instantiation)</a>
<ul>
<li><a href="#orge1140cd">2.2.1. Positional association</a></li>
<li><a href="#org2816dec">2.2.2. Named association</a></li>
</ul>
</li>
<li><a href="#orge0c0661">2.3. Parameters</a>
<ul>
<li><a href="#orgdd61470">2.3.1. Definition inside a module declaration</a></li>
<li><a href="#org52a7b68">2.3.2. Usage when instantiating a module</a></li>
<li><a href="#org8922bec">2.3.3. Local Parameters</a></li>
</ul>
</li>
<li><a href="#orgf4729db">2.4. Modules Inside Modules</a>
<ul>
<li><a href="#org1520c22">2.4.1. Using modules inside other modules</a></li>
<li><a href="#orgaa022a1">2.4.2. Generating many module instances at once (generate)</a></li>
</ul>
</li>
<li><a href="#orgd24d1d3">2.5. Concurrent assignment (השמה של ערכים מקבילים/ברי שינוי) to wires inside modules</a>
<ul>
<li><a href="#org82a6639">2.5.1. Syntax</a></li>
</ul>
</li>
<li><a href="#orgeaa7e11">2.6. Procedular Blocks (הרצה סדרתית של הצהרות בתוך מודול)</a>
<ul>
<li><a href="#org4f9e593">2.6.1. Definition and types</a></li>
<li><a href="#org3cfb4fa">2.6.2. always<sub>comb</sub></a></li>
<li><a href="#org24dcefe">2.6.3. Complete assignments</a></li>
</ul>
</li>
</ul>
</li>
<li><a href="#org3439c04">3. Data Types and Values</a>
<ul>
<li><a href="#orgc932b95">3.1. SystemVerilog Logic Values</a></li>
<li><a href="#org6ced58c">3.2. 1-bit wires (logic)</a></li>
<li><a href="#orgdc37e62">3.3. Vectors</a>
<ul>
<li><a href="#org7d4b5f2">3.3.1. Vector Operations</a></li>
<li><a href="#org4caaa3b">3.3.2. Repeated Signals</a></li>
<li><a href="#orgfe25fac">3.3.3. A Working Example (Implementing Unsigned Extension)</a></li>
</ul>
</li>
<li><a href="#org6587bcc">3.4. Integer Literals</a>
<ul>
<li><a href="#orgbd75853">3.4.1. Available number bases (<radix> values)</a></li>
<li><a href="#org1b231d4">3.4.2. Default settings</a></li>
<li><a href="#orgbc26635">3.4.3. Examples</a></li>
</ul>
</li>
<li><a href="#org1afb700">3.5. Blocking and non-blocking assignment</a>
<ul>
<li><a href="#org7a86e76">3.5.1. Blocking assignment</a></li>
<li><a href="#orge9e7487">3.5.2. Non-blocking assignment</a></li>
</ul>
</li>
<li><a href="#org1c3fc1a">3.6. enum</a></li>
</ul>
</li>
<li><a href="#orgb85c557">4. Operations and Conditions</a>
<ul>
<li><a href="#org034379e">4.1. Logic Gates (built-in)</a>
<ul>
<li><a href="#org36d671c">4.1.1. Example implementation of a half hadder</a></li>
</ul>
</li>
<li><a href="#org461b337">4.2. Operators (built-in)</a>
<ul>
<li><a href="#orgfa1cb95">4.2.1. Bitwise Operators</a></li>
<li><a href="#org0f6eba6">4.2.2. Shift</a></li>
<li><a href="#org1954c33">4.2.3. Operator Precedence</a></li>
</ul>
</li>
<li><a href="#orgc36435c">4.3. Logical Operators</a>
<ul>
<li><a href="#orgbfabb9c">4.3.1. Relational Operators</a></li>
<li><a href="#org90439f1">4.3.2. Logical Operators</a></li>
<li><a href="#orgc16e287">4.3.3. Operator Precedence</a></li>
</ul>
</li>
<li><a href="#orgf352d84">4.4. Conditional Statements</a>
<ul>
<li><a href="#orgf8f76ae">4.4.1. if</a></li>
<li><a href="#orgcc52ef9">4.4.2. case</a></li>
</ul>
</li>
</ul>
</li>
<li><a href="#org3f385ce">5. Synchronous logic and assignments (always<sub>ff</sub>)</a>
<ul>
<li><a href="#org0214903">5.1. Positive Edge (דגימה בעליית שעון)</a></li>
<li><a href="#org9f2e057">5.2. Synchronous Reset</a></li>
<li><a href="#org3fe6df0">5.3. Asynchronous Reset</a></li>
<li><a href="#orgf02f052">5.4. Implementing a Flip-Flop with Reset</a></li>
</ul>
</li>
<li><a href="#org064337e">6. Finite State Machines</a>
<ul>
<li><a href="#org399e76c">6.1. FSM template</a></li>
<li><a href="#orgde10e1c">6.2. Next state recipe for synchronous logic</a></li>
<li><a href="#orgd062351">6.3. FSM - (Mealy) Asynchronous Logic</a></li>
<li><a href="#org0775f74">6.4. FSM - (Moore) Asynchronous Logic</a></li>
</ul>
</li>
<li><a href="#org18b02fd">7. Testbench</a>
<ul>
<li><a href="#org04a6f56">7.1. Unit Under Test (UUT)</a></li>
<li><a href="#org69d20d1">7.2. Generating input values</a></li>
<li><a href="#org097321f">7.3. Repeat Loop</a></li>
<li><a href="#org9dea553">7.4. Synchronous logic: Generating a Clock Signal</a></li>
<li><a href="#org5190f0a">7.5. Synchronous logic: Wait X clock cycles</a></li>
<li><a href="#org2d7fd4b">7.6. How to Debug a FSM</a></li>
</ul>
</li>
</ul>
</div>
</div>
<div id="outline-container-orgb5f89d6" class="outline-2">
<h2 id="orgb5f89d6"><span class="section-number-2">1.</span> Compile/Run</h2>
<div class="outline-text-2" id="text-1">
</div>
<div id="outline-container-org0ed20bb" class="outline-3">
<h3 id="org0ed20bb"><span class="section-number-3">1.1.</span> TL;DR</h3>
<div class="outline-text-3" id="text-1-1">
<ol class="org-ol">
<li><code>cd</code> to folder</li>
<li><code>vlib work</code> on first run</li>
<li><code>vlog <filename>.sv</code> to compile all relevant .sv files</li>
<li><code>vsim <testbench-name></code> to run your file (usually a testbench)</li>
<li><code>add wave sim:/<testbench-name>/uut/*</code></li>
<li>Run your simulation using either:
<ol class="org-ol">
<li><code>run <N></code> to run for <N> nanoseconds</li>
<li><code>run -all</code> to automatically stop testbench when completed</li>
</ol></li>
<li><code>vlog</code> to recompile relevant modules as needed</li>
<li><code>restart -f</code> to restart your simulation</li>
</ol>
<p>
To run .tcl scripts, use <code>source <script-name>.tcl</code>.
</p>
</div>
</div>
<div id="outline-container-org40a7bca" class="outline-3">
<h3 id="org40a7bca"><span class="section-number-3">1.2.</span> Detailed Explanation:</h3>
<div class="outline-text-3" id="text-1-2">
<ol class="org-ol">
<li><span class="underline">Navigate to your project directory using <code>cd</code>.</span> <br />
The path should:
<ul class="org-ul">
<li>Use these slashes: ’/’</li>
<li>Use English characters</li>
<li>Not have any spaces (alternatively, it use quotes “”) <br /></li>
</ul></li>
<li><span class="underline">Create a ’work’ library using the command <code>vlib work</code>.</span>
<ul class="org-ul">
<li>This is supposedly mandatory.</li>
<li>Only needs to be performed while running your project for the first time. <br /></li>
</ul></li>
<li><span class="underline">Compile your .sv files using <code>vlog</code></span>
<ul class="org-ul">
<li>If some files depend on modules from other files,
You will have to compile these files first. <br /></li>
</ul></li>
<li><span class="underline">When running testbench, recompile relevant modules as needed using <code>vlog</code></span>
<ul class="org-ul">
<li>You only need to recompile the relevant modules.</li>
<li>No need to recompile the testbench itself or any other modules.</li>
</ul></li>
</ol>
</div>
</div>
</div>
<div id="outline-container-org8c4e125" class="outline-2">
<h2 id="org8c4e125"><span class="section-number-2">2.</span> Modules</h2>
<div class="outline-text-2" id="text-2">
</div>
<div id="outline-container-org43e5310" class="outline-3">
<h3 id="org43e5310"><span class="section-number-3">2.1.</span> Defining a module</h3>
<div class="outline-text-3" id="text-2-1">
<ul class="org-ul">
<li>Everything you write in SystemVerilog must be inside a module.</li>
<li><p>
A module is a fundemental building block that receives inputs and generates outputs.
</p>
<div id="org4440c18" class="figure">
<p><img src="System_Verilog_Building_Blocks/2023-03-23_19-21-38_screenshot.png" alt="2023-03-23_19-21-38_screenshot.png" />
</p>
</div>
<p>
Here’s an example module:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">[a,b] -> [my_module] -> [result = (a AND b)]</span>
<span style="color: #0000FF;">module</span> <span style="color: #006699;">my_module</span>(
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Input and Output Declaration</span>
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">a</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">b</span>,
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">result</span>);
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Declarations of "f"</span>
<span style="color: #0000FF;">assign</span> result = a & b;
<span style="color: #0000FF;">endmodule</span>
</pre>
</div></li>
</ul>
</div>
</div>
<div id="outline-container-orgf7da603" class="outline-3">
<h3 id="orgf7da603"><span class="section-number-3">2.2.</span> Creating module instances (instantiation)</h3>
<div class="outline-text-3" id="text-2-2">
</div>
<div id="outline-container-orge1140cd" class="outline-4">
<h4 id="orge1140cd"><span class="section-number-4">2.2.1.</span> Positional association</h4>
<div class="outline-text-4" id="text-2-2-1">
<p>
Define an instance of a module according to its argument positions, as such:
</p>
<div class="org-src-container">
<pre class="src src-verilog">module_name <span style="color: #006699;">instance_name</span> (
my_input1,
...,
my_inputN,
my_out1,
...,
my_outM
);
</pre>
</div>
</div>
</div>
<div id="outline-container-org2816dec" class="outline-4">
<h4 id="org2816dec"><span class="section-number-4">2.2.2.</span> Named association</h4>
<div class="outline-text-4" id="text-2-2-2">
<p>
Modules can also be instantiated using its arguments’ names explicitly:
</p>
<div class="org-src-container">
<pre class="src src-verilog">module_name <span style="color: #006699;">instance_name2</span> (
.<span style="color: #006699;">in1</span>(my_input1)),
...,
.<span style="color: #006699;">inN</span>(my_inputN),
.<span style="color: #006699;">out1</span>(my_output1),
...,
.<span style="color: #006699;">outM</span>(my_outputM)
)
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-orge0c0661" class="outline-3">
<h3 id="orge0c0661"><span class="section-number-3">2.3.</span> Parameters</h3>
<div class="outline-text-3" id="text-2-3">
<ul class="org-ul">
<li>Allows to pass parameters to a module per-instantiation.</li>
<li><i>Note: different from logic inputs and outputs.</i></li>
</ul>
</div>
<div id="outline-container-orgdd61470" class="outline-4">
<h4 id="orgdd61470"><span class="section-number-4">2.3.1.</span> Definition inside a module declaration</h4>
<div class="outline-text-4" id="text-2-3-1">
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">some_module</span> (
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">in1</span>
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">out1</span>
);
<span style="color: #6434A3;">parameter</span> <span style="color: #BA36A5;">param1</span> = <span style="color: #D0372D;">1</span>; <span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">1 is a default value</span>
<span style="color: #6434A3;">parameter</span> <span style="color: #BA36A5;">param1</span> = <span style="color: #D0372D;">2</span>;
<span style="color: #6434A3;">parameter</span> <span style="color: #BA36A5;">param1</span> = <span style="color: #D0372D;">3</span>;
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
</div>
</div>
<div id="outline-container-org52a7b68" class="outline-4">
<h4 id="org52a7b68"><span class="section-number-4">2.3.2.</span> Usage when instantiating a module</h4>
<div class="outline-text-4" id="text-2-3-2">
<p>
A module that shifts a number left N times.
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">shift_N</span> (
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">out</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">a</span>
);
<span style="color: #6434A3;">parameter</span> <span style="color: #BA36A5;">N</span> = <span style="color: #D0372D;">1</span>;
<span style="color: #0000FF;">always_comb</span> <span style="color: #6434A3;">begin</span>
out = a << N;
<span style="color: #6434A3;">end</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<p>
Here are some usage examples:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">multiple_shifts</span> (
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">a</span>,
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">b</span>,
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">c</span>
);
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Output a 2 shift result to b</span>
shift_N #(.<span style="color: #006699;">N</span>(<span style="color: #D0372D;">2</span>)) <span style="color: #006699;">shift_2</span>(.<span style="color: #006699;">a</span>(a), .<span style="color: #006699;">out</span>(b));
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Output a 3 shift result to c</span>
shift_N #(.<span style="color: #006699;">N</span>(<span style="color: #D0372D;">3</span>)) <span style="color: #006699;">shift_3</span>(.<span style="color: #006699;">a</span>(a), .<span style="color: #006699;">out</span>(c));
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
</div>
</div>
<div id="outline-container-org8922bec" class="outline-4">
<h4 id="org8922bec"><span class="section-number-4">2.3.3.</span> Local Parameters</h4>
<div class="outline-text-4" id="text-2-3-3">
<p>
Store constant values inside a module.
These cannot be changed or passed to an instance module.
</p>
<p>
Here’s an example:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">my_module</span>(...);
<span style="color: #6434A3;">localparam</span> <span style="color: #BA36A5;">N</span> = <span style="color: #D0372D;">2</span>'b11;
<span style="color: #6434A3;">localparam</span> <span style="color: #BA36A5;">NUM_OF_CYCLES</span> = <span style="color: #D0372D;">10</span>;
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-orgf4729db" class="outline-3">
<h3 id="orgf4729db"><span class="section-number-3">2.4.</span> Modules Inside Modules</h3>
<div class="outline-text-3" id="text-2-4">
</div>
<div id="outline-container-org1520c22" class="outline-4">
<h4 id="org1520c22"><span class="section-number-4">2.4.1.</span> Using modules inside other modules</h4>
<div class="outline-text-4" id="text-2-4-1">
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Mux that takes 2-bit inputs and outputs a 2-bit result</span>
<span style="color: #0000FF;">module</span> <span style="color: #006699;">mux2to1_2bit</span> (
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">1</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">O</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">1</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">A</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">1</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">B</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">S</span>
);
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Use instances of existing 1-bit input muxes</span>
mux2to1_1bit <span style="color: #006699;">mux1</span>(.<span style="color: #006699;">O</span>(O[<span style="color: #D0372D;">1</span>]), .<span style="color: #006699;">S</span>(S), .<span style="color: #006699;">A</span>(A[<span style="color: #D0372D;">1</span>]), .<span style="color: #006699;">B</span>(B[<span style="color: #D0372D;">1</span>]));
mux2to1_1bit <span style="color: #006699;">mux0</span>(.<span style="color: #006699;">O</span>(O[<span style="color: #D0372D;">0</span>]), .<span style="color: #006699;">S</span>(S), .<span style="color: #006699;">A</span>(A[<span style="color: #D0372D;">0</span>]), .<span style="color: #006699;">B</span>(B[<span style="color: #D0372D;">0</span>]));
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
</div>
</div>
<div id="outline-container-orgaa022a1" class="outline-4">
<h4 id="orgaa022a1"><span class="section-number-4">2.4.2.</span> Generating many module instances at once (generate)</h4>
<div class="outline-text-4" id="text-2-4-2">
<p>
You can use the <code>generate</code> command to create many module instances at once:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">mux2to1_32bit</span> (
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">31</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">O</span>, <span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">32-bit output</span>
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">31</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">A</span>, <span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">32-bit input A</span>
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">31</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">B</span>, <span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">32-bit input B</span>
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">S</span>
);
<span style="color: #6434A3;">genvar</span> <span style="color: #BA36A5;">i</span>;
<span style="color: #0000FF;">generate</span>
<span style="color: #0000FF;">for</span> (i = <span style="color: #D0372D;">0</span>; i < <span style="color: #D0372D;">32</span>; i++)
<span style="color: #6434A3;">begin</span>
mux2to1 <span style="color: #006699;">mux_inst</span>(.<span style="color: #006699;">O</span>(O[i]), .<span style="color: #006699;">S</span>(S), .<span style="color: #006699;">A</span>(A[i]), .<span style="color: #006699;">B</span>(B[i]));
<span style="color: #6434A3;">end</span>
<span style="color: #0000FF;">endgenerate</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-orgd24d1d3" class="outline-3">
<h3 id="orgd24d1d3"><span class="section-number-3">2.5.</span> Concurrent assignment (השמה של ערכים מקבילים/ברי שינוי) to wires inside modules</h3>
<div class="outline-text-3" id="text-2-5">
<p>
Connect a wire to some combinatorical logic or another wire.
</p>
</div>
<div id="outline-container-org82a6639" class="outline-4">
<h4 id="org82a6639"><span class="section-number-4">2.5.1.</span> Syntax</h4>
<div class="outline-text-4" id="text-2-5-1">
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">A simple assignment from one wire to another</span>
<span style="color: #0000FF;">module</span> <span style="color: #006699;">pass_same_value</span>(
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">Z</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">A</span>
);
<span style="color: #0000FF;">assign</span> Z = A;
<span style="color: #0000FF;">endmodule</span>
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">Assigning some concurring calculation to wire</span>
<span style="color: #0000FF;">module</span> <span style="color: #006699;">and_module</span> (
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">Z</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">A</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">B</span>
);
<span style="color: #0000FF;">assign</span> Z = A & B;
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<p>
An explicit value can also be used.
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">signal</span>;
<span style="color: #0000FF;">assign</span> signal = <span style="color: #D0372D;">1</span>'b0;
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-orgeaa7e11" class="outline-3">
<h3 id="orgeaa7e11"><span class="section-number-3">2.6.</span> Procedular Blocks (הרצה סדרתית של הצהרות בתוך מודול)</h3>
<div class="outline-text-3" id="text-2-6">
</div>
<div id="outline-container-org4f9e593" class="outline-4">
<h4 id="org4f9e593"><span class="section-number-4">2.6.1.</span> Definition and types</h4>
<div class="outline-text-4" id="text-2-6-1">
<p>
All statements inside a procedural block are executed sequentially.
</p>
<p>
There are two procedural constructs in Verilog:
</p>
<ul class="org-ul">
<li><code>initial</code></li>
<li><p>
<code>always_comb</code>
</p>
<p>
We will only use <code>initial</code> in simulations (testbenches).
For regular modules, we use <code>always_comb</code>.
</p></li>
</ul>
</div>
</div>
<div id="outline-container-org3cfb4fa" class="outline-4">
<h4 id="org3cfb4fa"><span class="section-number-4">2.6.2.</span> always<sub>comb</sub></h4>
<div class="outline-text-4" id="text-2-6-2">
<p>
Executes statements in a loop.
Used for combinatorical logic implementation.
</p>
<p>
Here’s a working example:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">and_module</span>(
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">Z</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">A</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">B</span>
);
<span style="color: #0000FF;">always_comb</span> <span style="color: #6434A3;">begin</span>
Z = A & B;
<span style="color: #6434A3;">end</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<p>
You can use <a href="#orgf352d84">conditional statements</a> inside of a procedural block.
</p>
</div>
</div>
<div id="outline-container-org24dcefe" class="outline-4">
<h4 id="org24dcefe"><span class="section-number-4">2.6.3.</span> Complete assignments</h4>
<div class="outline-text-4" id="text-2-6-3">
<p>
<b>Note:</b> <code>always_comb</code> should NOT be used for memory elements!
</p>
<ul class="org-ul">
<li>If a signal is not assigned in a certain flow, a memory element is implicitly created to preserve the previous value.</li>
<li>Usually, this is a bug.</li>
<li>Always use complete assignments.</li>
</ul>
</div>
<ol class="org-ol">
<li><a id="org9f41166"></a>“if” statements<br />
<div class="outline-text-5" id="text-2-6-3-1">
<p>
Use “else”
</p>
</div>
</li>
<li><a id="org85b325a"></a>“case” statements<br />
<div class="outline-text-5" id="text-2-6-3-2">
<p>
Use “default”
</p>
</div>
</li>
<li><a id="orga9c0cc9"></a>General solution<br />
<div class="outline-text-5" id="text-2-6-3-3">
<p>
Use default assignments
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">always_comb</span> <span style="color: #6434A3;">begin</span>
Q = <span style="color: #D0372D;">1</span>'b0;
<span style="color: #0000FF;">if</span> (sel == <span style="color: #D0372D;">1</span>'b1) <span style="color: #6434A3;">begin</span>
Q = A;
<span style="color: #6434A3;">end</span>
<span style="color: #6434A3;">end</span>
</pre>
</div>
<div id="orge32bb82" class="figure">
<p><img src="Modules/2023-06-09_22-56-05_screenshot.png" alt="2023-06-09_22-56-05_screenshot.png" />
</p>
</div>
</div>
</li>
</ol>
</div>
</div>
</div>
<div id="outline-container-org3439c04" class="outline-2">
<h2 id="org3439c04"><span class="section-number-2">3.</span> Data Types and Values</h2>
<div class="outline-text-2" id="text-3">
</div>
<div id="outline-container-orgc932b95" class="outline-3">
<h3 id="orgc932b95"><span class="section-number-3">3.1.</span> SystemVerilog Logic Values</h3>
<div class="outline-text-3" id="text-3-1">
<p>
In SystemVerilog, a bit can take the following logical values:
</p>
<table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
<colgroup>
<col class="org-left" />
<col class="org-left" />
</colgroup>
<thead>
<tr>
<th scope="col" class="org-left">Logic Value</th>
<th scope="col" class="org-left">Meaning</th>
</tr>
</thead>
<tbody>
<tr>
<td class="org-left">0</td>
<td class="org-left">zero / logic low / false / ground</td>
</tr>
<tr>
<td class="org-left">1</td>
<td class="org-left">one / logic high / true / power</td>
</tr>
<tr>
<td class="org-left">x</td>
<td class="org-left">not initialized or collision</td>
</tr>
<tr>
<td class="org-left">z</td>
<td class="org-left">unconnected</td>
</tr>
</tbody>
</table>
</div>
</div>
<div id="outline-container-org6ced58c" class="outline-3">
<h3 id="org6ced58c"><span class="section-number-3">3.2.</span> 1-bit wires (logic)</h3>
<div class="outline-text-3" id="text-3-2">
<p>
The <code>logic</code> data type represents a wire (1 bit):
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">a</span>,<span style="color: #BA36A5;">b</span>,<span style="color: #BA36A5;">c</span>,<span style="color: #BA36A5;">d</span>,<span style="color: #BA36A5;">e</span>;
</pre>
</div>
<div id="org0cf255d" class="figure">
<p><img src="Data_Types/2023-03-23_19-42-28_screenshot.png" alt="2023-03-23_19-42-28_screenshot.png" />
</p>
</div>
</div>
</div>
<div id="outline-container-orgdc37e62" class="outline-3">
<h3 id="orgdc37e62"><span class="section-number-3">3.3.</span> Vectors</h3>
<div class="outline-text-3" id="text-3-3">
<p>
Declaration of an 8-bit logic vector:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">7</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">w1</span>; <span style="color: #8D8D84;">//</span><span style="color: #8D8D84; font-style: italic;">w1[7] is the MSB</span>
</pre>
</div>
<p>
Here’s how you’d describe the “selector” wires in a mux module declaration:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">mux4tol</span>(
<span style="color: #6434A3;">output</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">O</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">D0</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">D1</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">D2</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">D3</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">E</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">1</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">S</span>
);
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">declarations</span>
<span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">description of a mux</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<div id="org5041075" class="figure">
<p><img src="Data_Types_and_Values/2023-03-23_22-54-02_screenshot.png" alt="2023-03-23_22-54-02_screenshot.png" />
</p>
</div>
</div>
<div id="outline-container-org7d4b5f2" class="outline-4">
<h4 id="org7d4b5f2"><span class="section-number-4">3.3.1.</span> Vector Operations</h4>
<div class="outline-text-4" id="text-3-3-1">
<ul class="org-ul">
<li><p>
Bit select:
</p>
<div class="org-src-container">
<pre class="src src-verilog"> w1[<span style="color: #D0372D;">3</span>]
</pre>
</div></li>
<li><p>
Range select:
</p>
<div class="org-src-container">
<pre class="src src-verilog"> w1[<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">2</span>]
</pre>
</div></li>
<li><p>
Pack:
</p>
<div class="org-src-container">
<pre class="src src-verilog"> vec = {x, y, z};
</pre>
</div></li>
<li><p>
Unpack:
</p>
<div class="org-src-container">
<pre class="src src-verilog"> {carry, sum} = vec[<span style="color: #D0372D;">1</span>:<span style="color: #D0372D;">0</span>];
</pre>
</div></li>
</ul>
</div>
</div>
<div id="outline-container-org4caaa3b" class="outline-4">
<h4 id="org4caaa3b"><span class="section-number-4">3.3.2.</span> Repeated Signals</h4>
<div class="outline-text-4" id="text-3-3-2">
<p>
A signal can be repeated \(n\) times in this manner:
</p>
<div class="org-src-container">
<pre class="src src-verilog">vec = {<span style="color: #D0372D;">16</span>{x}} <span style="color: #8D8D84;">// </span><span style="color: #8D8D84; font-style: italic;">16 copies of x</span>
</pre>
</div>
</div>
</div>
<div id="outline-container-orgfe25fac" class="outline-4">
<h4 id="orgfe25fac"><span class="section-number-4">3.3.3.</span> A Working Example (Implementing Unsigned Extension)</h4>
<div class="outline-text-4" id="text-3-3-3">
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">7</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">out</span>;
<span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">A</span>;
out = {{<span style="color: #D0372D;">4</span>{<span style="color: #D0372D;">1</span>'b0}}, A[<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>]};
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-org6587bcc" class="outline-3">
<h3 id="org6587bcc"><span class="section-number-3">3.4.</span> Integer Literals</h3>
<div class="outline-text-3" id="text-3-4">
<p>
<span class="underline">Format</span>: <b><width’><signed><radix> value</b>
</p>
<p>
You can use this format to generate:
</p>
<ul class="org-ul">
<li>Multiple bit integers (<code><width'></code>)</li>
<li>Two’s complement negative numbers (<code><signed></code>)</li>
<li>Write a number in base 2,8,10 or 16 (<code><radix></code>)</li>
</ul>
</div>
<div id="outline-container-orgbd75853" class="outline-4">
<h4 id="orgbd75853"><span class="section-number-4">3.4.1.</span> Available number bases (<radix> values)</h4>
<div class="outline-text-4" id="text-3-4-1">
<ul class="org-ul">
<li>Binary (<code>b</code> or <code>B</code>)</li>
<li>Octal (<code>o</code> or <code>O</code>)</li>
<li>Decimal (<code>d</code> or <code>D</code>)</li>
<li>Hexadecimal (<code>g</code> or <code>G</code>)</li>
</ul>
</div>
</div>
<div id="outline-container-org1b231d4" class="outline-4">
<h4 id="org1b231d4"><span class="section-number-4">3.4.2.</span> Default settings</h4>
<div class="outline-text-4" id="text-3-4-2">
<ul class="org-ul">
<li>Width = 32</li>
<li>Unsigned</li>
<li>Radix = Decimal</li>
</ul>
</div>
</div>
<div id="outline-container-orgbc26635" class="outline-4">
<h4 id="orgbc26635"><span class="section-number-4">3.4.3.</span> Examples</h4>
<div class="outline-text-4" id="text-3-4-3">
<ul class="org-ul">
<li><code>1'b0</code> - one bit, unsigned, value of zero</li>
<li><code>12'hAD1</code> - 12 bits, unsigned, value of 0xAD1</li>
<li><code>12'b1010_1101_0001</code> - 12 bits, unsigned, value of 0xAD1</li>
<li><code>14</code> - defaults: 32 bits, unsigned, value of 14</li>
<li><code>-14</code> - 32 bits, signed, value of -14</li>
</ul>
</div>
</div>
</div>
<div id="outline-container-org1afb700" class="outline-3">
<h3 id="org1afb700"><span class="section-number-3">3.5.</span> Blocking and non-blocking assignment</h3>
<div class="outline-text-3" id="text-3-5">
</div>
<div id="outline-container-org7a86e76" class="outline-4">
<h4 id="org7a86e76"><span class="section-number-4">3.5.1.</span> Blocking assignment</h4>
<div class="outline-text-4" id="text-3-5-1">
<p>
Acts much like in traditional programming languages.
The whole statemnt is done before control passes on to the next statement.
</p>
<p>
In <code>always_comb</code>, we use a <b>blocking</b> assigment:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">a</span>, <span style="color: #BA36A5;">in</span>;
<span style="color: #0000FF;">always_comb</span> <span style="color: #6434A3;">begin</span>
a = in;
<span style="color: #6434A3;">end</span>
</pre>
</div>
</div>
</div>
<div id="outline-container-orge9e7487" class="outline-4">
<h4 id="orge9e7487"><span class="section-number-4">3.5.2.</span> Non-blocking assignment</h4>
<div class="outline-text-4" id="text-3-5-2">
<p>
Evaluates all the right-hand sides for the current time unit.
Assigns the left-hand sides at the end of the procedural block.
</p>
<p>
Basically, allows behavior of a shift register.
</p>
<p>
This is how you’d implement a shift behavior between Flip-Flops:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">shifter</span> (
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">in</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">clk</span>
);
<span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">A</span>, <span style="color: #BA36A5;">B</span>, <span style="color: #BA36A5;">C</span>;
<span style="color: #0000FF;">always_ff</span> <span style="color: #6434A3;">@</span>(<span style="color: #0000FF;">posedge</span> clk) <span style="color: #6434A3;">begin</span>
A <= in;
B <= A;
C <= B;
<span style="color: #6434A3;">end</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<div id="org2b07487" class="figure">
<p><img src="Data_Types_and_Values/2023-06-10_01-06-38_screenshot.png" alt="2023-06-10_01-06-38_screenshot.png" />
</p>
</div>
<p>
And this is what happens when you accidentally use blocking assignments instead:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #0000FF;">module</span> <span style="color: #006699;">bad_shifter</span> (
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">in</span>,
<span style="color: #6434A3;">input</span> <span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">clk</span>
);
<span style="color: #6434A3;">logic</span> <span style="color: #BA36A5;">A</span>, <span style="color: #BA36A5;">B</span>, <span style="color: #BA36A5;">C</span>;
<span style="color: #0000FF;">always_ff</span> <span style="color: #6434A3;">@</span>(<span style="color: #0000FF;">posedge</span> clk) <span style="color: #6434A3;">begin</span>
A = in;
B = A;
C = B;
<span style="color: #6434A3;">end</span>
<span style="color: #0000FF;">endmodule</span>
</pre>
</div>
<div id="orgc37745c" class="figure">
<p><img src="Data_Types_and_Values/2023-06-10_01-09-24_screenshot.png" alt="2023-06-10_01-09-24_screenshot.png" />
</p>
</div>
</div>
</div>
</div>
<div id="outline-container-org1c3fc1a" class="outline-3">
<h3 id="org1c3fc1a"><span class="section-number-3">3.6.</span> enum</h3>
<div class="outline-text-3" id="text-3-6">
<p>
An enum type defines a set of named values.
We will use <code>enum</code> for FSM state declaration:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">7</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">out</span>;
<span style="color: #6434A3;">logic</span> [<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>] <span style="color: #BA36A5;">A</span>;
out = {{<span style="color: #D0372D;">4</span>{<span style="color: #D0372D;">1</span>'b0}}, A[<span style="color: #D0372D;">3</span>:<span style="color: #D0372D;">0</span>]};
</pre>
</div>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #6434A3;">typedef</span> enu​m {idle_st, state1, state2} state_type;
</pre>
</div>
</div>
</div>
</div>
<div id="outline-container-orgb85c557" class="outline-2">
<h2 id="orgb85c557"><span class="section-number-2">4.</span> Operations and Conditions</h2>
<div class="outline-text-2" id="text-4">
</div>
<div id="outline-container-org034379e" class="outline-3">
<h3 id="org034379e"><span class="section-number-3">4.1.</span> Logic Gates (built-in)</h3>
<div class="outline-text-3" id="text-4-1">
<p>
The following logic gates are available for direct instantiation:
</p>
<ul class="org-ul">
<li>and</li>
<li>or</li>
<li>not</li>
<li>xor</li>
<li>nand</li>
<li>nor</li>
<li>xnor</li>
</ul>
<p>
Syntax:
</p>
<div class="org-src-container">
<pre class="src src-verilog"><span style="color: #006699;">gateName</span>(<span style="color: #6434A3;">output</span>, <span style="color: #BA36A5;">input1</span>, <<span style="color: #BA36A5;">optional_input2</span>>)
</pre>
</div>
</div>
<div id="outline-container-org36d671c" class="outline-4">
<h4 id="org36d671c"><span class="section-number-4">4.1.1.</span> Example implementation of a half hadder</h4>
<div class="outline-text-4" id="text-4-1-1">
<div class="org-src-container">