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[nrf noup] boards: add nrf54l15/nrf54l15/cpuapp/ns as board variant
This commit adds the nRF54l15//nrf54l15/cpuapp/ns board variant to sdk-zephyr. It allows to build nRF54l15pdk with TF-M in nRF Connect SDK. This is done as a nrf noup patch as the out-of-tree board extension feature is not available. When zephyrproject-rtos/zephyr#69548 is completed, then this commit can be reverted and the variant be placed in sdk-nrf repository. Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no> Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no> (cherry picked from commit c8cc663)
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‎boards/nordic/nrf54l15pdk/Kconfig‎

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@@ -11,3 +11,46 @@ config BOARD_ENABLE_DCDC
1111
default y
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endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP
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if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
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# TODO: Remove the options bellow when (NCSDK-25023) is done
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config NRF_SPU_FLASH_REGION_SIZE
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hex
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default 0x4000
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# This option does not apply to 54, but we pretend the HW has this limitation
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# for now for easier porting. NCSDK-25023
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help
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FLASH region size for the NRF_SPU peripheral. For nrf54 the
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region size is configurable per-region so this option does
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not apply.
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config NRF_SPU_FLASH_REGION_ALIGNMENT
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hex
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default 0x4000
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# This option does not apply to 54, but we pretend the HW has this limitation
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# for now for easier porting. NCSDK-25023
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help
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FLASH region size for the NRF_SPU peripheral. For nrf54 the
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region size is configurable per-region so this option does
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not apply.
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config NRF_SPU_RAM_REGION_SIZE
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hex
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default 0x2000
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# This HW limitation does not apply to 54, but we pretend
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# it does for now for easier porting. NCSDK-25023
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help
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RAM region size for the NRF_SPU peripheral. For nrf54 the
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region size is configurable per-region so this option does
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not apply.
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config NRF_SPU_RAM_REGION_ALIGNMENT
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hex
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default 0x1000
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help
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RAM regions must be aligned to this value due to SPU HW
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limitations.
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endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS

‎boards/nordic/nrf54l15pdk/Kconfig.defconfig‎

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@@ -11,3 +11,21 @@ config ROM_START_OFFSET
1111
default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP
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if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
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config BT_CTLR
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default BT
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# By default, if we build for a Non-Secure version of the board,
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# enable building with TF-M as the Secure Execution Environment.
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config BUILD_WITH_TFM
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default y if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
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# By default, if we build with TF-M, instruct build system to
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# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
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config TFM_FLASH_MERGED_BINARY
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default y
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depends on BUILD_WITH_TFM
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endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS

‎boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk‎

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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF54L15PDK
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select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP
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select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP || BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
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select SOC_NRF54L15_ENGA_CPUFLPR if BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || \
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BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP

‎boards/nordic/nrf54l15pdk/board.cmake‎

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@@ -7,6 +7,14 @@ elseif (CONFIG_SOC_NRF54L15_ENGA_CPUFLPR)
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board_runner_args(jlink "--speed=4000")
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endif()
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if(BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS)
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set(TFM_PUBLIC_KEY_FORMAT "full")
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endif()
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if(CONFIG_TFM_FLASH_MERGED_BINARY)
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set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
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endif()
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nordic/nrf54l15pdk/board.yml‎

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@@ -6,6 +6,8 @@ board:
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variants:
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- name: xip
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cpucluster: cpuflpr
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- name: ns
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cpucluster: cpuapp
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revision:
1012
format: major.minor.patch
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default: "0.3.0"

‎boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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&pinctrl {
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uart20_default: uart20_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>,
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<NRF_PSEL(UART_RX, 1, 5)>;
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};
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};
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uart20_sleep: uart20_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>,
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<NRF_PSEL(UART_RX, 1, 5)>;
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low-power-enable;
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};
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};
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uart30_default: uart30_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RX, 0, 1)>;
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};
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};
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uart30_sleep: uart30_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RX, 0, 1)>;
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low-power-enable;
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};
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};
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};

‎boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/dts-v1/;
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#include <nordic/nrf54l15_cpuapp_ns.dtsi>
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#include "nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi"
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/ {
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chosen {
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zephyr,console = &uart20;
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/* TODO: NCSDK-24862: We don't support configuring RRAM and SRAM
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* regions in the DTS file yet. The partition manager configures
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* these regions now.
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*/
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zephyr,shell-uart = &uart20;
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zephyr,flash = &rram0;
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zephyr,sram = &sram0;
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zephyr,ieee802154 = &ieee802154;
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};
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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label = "Green LED 0";
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};
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led1: led_1 {
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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label = "Green LED 1";
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};
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led2: led_2 {
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gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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label = "Green LED 2";
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};
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led3: led_3 {
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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label = "Green LED 3";
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 0";
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zephyr,code = <INPUT_KEY_0>;
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};
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button1: button_1 {
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gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 1";
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zephyr,code = <INPUT_KEY_1>;
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};
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button2: button_2 {
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gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 2";
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zephyr,code = <INPUT_KEY_2>;
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};
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button3: button_3 {
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gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 3";
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zephyr,code = <INPUT_KEY_3>;
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};
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};
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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led3 = &led3;
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sw0 = &button0;
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sw1 = &button1;
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sw2 = &button2;
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sw3 = &button3;
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};
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};
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&uart20 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&uart20_default>;
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pinctrl-1 = <&uart20_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&uart30 {
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/* Disable so that TF-M can use this UART */
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status = "disabled";
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current-speed = <115200>;
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pinctrl-0 = <&uart30_default>;
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pinctrl-1 = <&uart30_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&grtc {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};

‎boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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identifier: nrf54l15pdk/nrf54l15/cpuapp/ns
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name: nRF54l15-PDK-nRF54l15-Application-Non-Secure
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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ram: 256
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flash: 1524
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supported:
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- adc
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- gpio
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- i2c
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- spi
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- counter
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- watchdog
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- adc
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- i2s

‎boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable TrustZone-M
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CONFIG_ARM_TRUSTZONE_M=y
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# This Board implies building Non-Secure firmware
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CONFIG_TRUSTED_EXECUTION_NONSECURE=y
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# Don't enable the cache in the non-secure image as it is a
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# secure-only peripheral on 54l
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CONFIG_CACHE_MANAGEMENT=n
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CONFIG_EXTERNAL_CACHE=n
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CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Start SYSCOUNTER on driver init
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CONFIG_NRF_GRTC_START_SYSCOUNTER=y

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