architecture-vawgan-vcc2016.json

{
	"mode": "VAWGAN",    
	"hwc": [513, 1, 1],
	"z_dim": 128,
	"y_dim": 10,
	"y_emb_dim": 128,
	"discriminator": {
        "merge_dim": 1024,
		"kernel": [[7, 1], [7, 1], [115, 1]],
		"stride": [[3, 1], [3, 1], [3, 1]],
		"output": [16, 32, 64],
		"l2-reg": 1e-6,
		"feature_layer": 1
    },
    "encoder": {
        "kernel": [[7, 1], [7, 1], [7, 1], [7, 1], [7, 1]],
		"stride": [[3, 1], [3, 1], [3, 1], [3, 1], [3, 1]],
		"output": [16, 32, 64, 128, 256],
		"l2-reg": 1e-6
	},
	"generator": {
        "hwc": [19, 1, 81],
		"merge_dim": 171,
		"kernel": [[9, 1], [7, 1], [7, 1], [1025, 1]],
		"stride": [[3, 1], [3, 1], [3, 1], [1, 1]],
		"output": [32, 16, 8, 1],
		"l2-reg": 1e-6
    },
	"training": {
        "datadir": ["./dataset/vcc2016/bin/*/SF1/100*.bin", "./dataset/vcc2016/bin/*/TM3/100*.bin"],
		"batch_size": 16,
		"epoch": 200,
		"lr": 1e-4,
		"beta1": 0.5,
		"beta2": 0.999,
        "nIterD": 5,
        "lambda": 10,
        "alpha": 50.0,
		"max_iter": 200000
	}
}