Refactor translation and reverse translation of PipelineEnableINTEL for loops and functions (#2171)

bowenxue-intel · web-flow · commit e68ddf71512a · 2023-10-09T12:05:30.000+02:00
Refactor SPIRVWriter to accept !disable_kernel_pipelining instead of !disable_loop_pipelining for function metadata, and !llvm.loop.intel.pipelining.disable instead of !llvm.loop.intel.pipelining.enable for loop metadata. Refactor SPIRVReader to emit !disable_kernel_pipelining instead of !disable_loop_pipelining for function metadata, and !llvm.loop.intel.pipelining.disable instead of !llvm.loop.intel.pipelining.enable for loop metadata. Relevant/Related intel/llvm PR: intel/llvm#11372
diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h
@@ -412,7 +412,7 @@ const static char PreferDSP[] = "prefer_dsp";
 const static char PropDSPPref[] = "propagate_dsp_preference";
 const static char InitiationInterval[] = "initiation_interval";
 const static char MaxConcurrency[] = "max_concurrency";
-const static char DisableLoopPipelining[] = "disable_loop_pipelining";
+const static char PipelineKernel[] = "pipeline_kernel";
 const static char IntelFPGAIPInterface[] = "ip_interface";
 } // namespace kSPIR2MD
 
diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
@@ -4544,8 +4544,8 @@ bool SPIRVToLLVM::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
   if (BF->hasDecorate(DecorationPipelineEnableINTEL)) {
     auto Literals = BF->getDecorationLiterals(DecorationPipelineEnableINTEL);
     std::vector<Metadata *> MetadataVec;
-    MetadataVec.push_back(ConstantAsMetadata::get(getInt32(M, !Literals[0])));
-    F->setMetadata(kSPIR2MD::DisableLoopPipelining,
+    MetadataVec.push_back(ConstantAsMetadata::get(getInt32(M, Literals[0])));
+    F->setMetadata(kSPIR2MD::PipelineKernel,
                    MDNode::get(*Context, MetadataVec));
   }
   return true;
diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
@@ -1029,12 +1029,11 @@ void LLVMToSPIRVBase::transFPGAFunctionMetadata(SPIRVFunction *BF,
       BF->addDecorate(new SPIRVDecorateMaxConcurrencyINTEL(BF, Invocations));
     }
   }
-  if (MDNode *DisableLoopPipelining =
-          F->getMetadata(kSPIR2MD::DisableLoopPipelining)) {
+  if (MDNode *PipelineKernel = F->getMetadata(kSPIR2MD::PipelineKernel)) {
     if (BM->isAllowedToUseExtension(
             ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes)) {
-      size_t Disable = getMDOperandAsInt(DisableLoopPipelining, 0);
-      BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, !Disable));
+      size_t Pipeline = getMDOperandAsInt(PipelineKernel, 0);
+      BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, Pipeline));
     }
   }
 
diff --git a/test/extensions/INTEL/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll b/test/extensions/INTEL/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll
@@ -10,7 +10,7 @@
 ;;     intel::loop_fuse_independent(3),
 ;;     intel::initiation_interval(10),
 ;;     intel::max_concurrency(12),
-;;     intel::disable_loop_pipelining]] void operator()() {}
+;;     intel::pipeline_kernel]] void operator()() {}
 ;; };
 ;;
 ;; template <typename name, typename Func>
@@ -62,23 +62,23 @@
 ; CHECK-LLVM-SAME: !stall_enable ![[ONEMD:[0-9]+]] !loop_fuse ![[FUSE:[0-9]+]]
 ; CHECK-LLVM-SAME: !initiation_interval ![[II:[0-9]+]]
 ; CHECK-LLVM-SAME: !max_concurrency ![[MAXCON:[0-9]+]]
-; CHECK-LLVM-SAME: !disable_loop_pipelining ![[ONEMD]]
+; CHECK-LLVM-SAME: !pipeline_kernel ![[ONEMD2:[0-9]+]]
 ; CHECK-LLVM-SAME: !max_work_group_size ![[MAXWG:[0-9]+]]
 ; CHECK-LLVM-SAME: !no_global_work_offset ![[OFFSET:[0-9]+]]
 ; CHECK-LLVM-SAME: !max_global_work_dim ![[ONEMD]] !num_simd_work_items ![[NUMSIMD:[0-9]+]]
 ; CHECK-LLVM-SAME: !scheduler_target_fmax_mhz ![[MAXMHZ:[0-9]+]]
 ; CHECK-LLVM-NOT: define spir_kernel void {{.*}}kernel_name2 {{.*}} !no_global_work_offset {{.*}}
 ; CHECK-LLVM: define spir_kernel void {{.*}}kernel_name3()
-; CHECK-LLVM-SAME: !disable_loop_pipelining ![[ONEMD2:[0-9]+]]
+; CHECK-LLVM-SAME: !pipeline_kernel ![[ONEMD]]
 ; CHECK-LLVM: ![[OFFSET]] = !{}
 ; CHECK-LLVM: ![[ONEMD]] = !{i32 1}
 ; CHECK-LLVM: ![[FUSE]] = !{i32 3, i32 1}
 ; CHECK-LLVM: ![[II]] = !{i32 10}
 ; CHECK-LLVM: ![[MAXCON]] = !{i32 12}
+; CHECK-LLVM: ![[ONEMD2]] = !{i32 0}
 ; CHECK-LLVM: ![[MAXWG]] = !{i32 1, i32 1, i32 1}
 ; CHECK-LLVM: ![[NUMSIMD]] = !{i32 8}
 ; CHECK-LLVM: ![[MAXMHZ]] = !{i32 1000}
-; CHECK-LLVM: ![[ONEMD2]] = !{i32 0}
 
 ; ModuleID = 'kernel-attrs.cpp'
 source_filename = "kernel-attrs.cpp"
@@ -91,7 +91,7 @@ target triple = "spir64-unknown-linux"
 $_ZN3FooclEv = comdat any
 
 ; Function Attrs: nounwind
-define spir_kernel void @_ZTSZ3barvE11kernel_name() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 !num_simd_work_items !5 !max_work_group_size !6 !max_global_work_dim !7 !no_global_work_offset !4 !stall_enable !7 !scheduler_target_fmax_mhz !12 !loop_fuse !13 !initiation_interval !14 !max_concurrency !15 !disable_loop_pipelining !7 {
+define spir_kernel void @_ZTSZ3barvE11kernel_name() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 !num_simd_work_items !5 !max_work_group_size !6 !max_global_work_dim !7 !no_global_work_offset !4 !stall_enable !7 !scheduler_target_fmax_mhz !12 !loop_fuse !13 !initiation_interval !14 !max_concurrency !15 !pipeline_kernel !16 {
 entry:
   %Foo = alloca %class._ZTS3Foo.Foo, align 1
   call void @llvm.lifetime.start.p0(i64 1, ptr %Foo) #4
@@ -135,7 +135,7 @@ entry:
 }
 
 ; Function Attrs: nounwind
-define spir_kernel void @_ZTSZ3barvE11kernel_name3() #0 !disable_loop_pipelining !16 {
+define spir_kernel void @_ZTSZ3barvE11kernel_name3() #0 !pipeline_kernel !7 {
 entry:
   %Foo = alloca %class._ZTS3Foo.Foo, align 1
   call void @llvm.lifetime.start.p0(i64 1, ptr %Foo) #4
diff --git a/test/extensions/INTEL/SPV_INTEL_kernel_attributes/spirv_fpga_function_decorations.ll b/test/extensions/INTEL/SPV_INTEL_kernel_attributes/spirv_fpga_function_decorations.ll
@@ -37,9 +37,9 @@ entry:
 !10 = !{i32 5919, i32 1}
 !11 = !{i32 5917, i32 2}
 
-; CHECK-SPV-IR: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !initiation_interval ![[II:[0-9]+]] !disable_loop_pipelining ![[DISABLE_LOOP_PIPELINING:[0-9]+]] {
+; CHECK-SPV-IR: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !initiation_interval ![[II:[0-9]+]] !pipeline_kernel ![[PIPELINE_KERNEL:[0-9]+]] {
 ; CHECK-SPV-IR-DAG: ![[II]] = !{i32 2}
-; CHECK-SPV-IR-DAG: ![[DISABLE_LOOP_PIPELINING]] = !{i32 0}
+; CHECK-SPV-IR-DAG: ![[PIPELINE_KERNEL]] = !{i32 1}
 
 ; CHECK-LLVM-NOT: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !spirv.Decorations ![[DecoListId:[0-9]+]] {
 ; CHECK-LLVM: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} {

Original file line number	Diff line number	Diff line change
`@@ -1029,12 +1029,11 @@ void LLVMToSPIRVBase::transFPGAFunctionMetadata(SPIRVFunction *BF,`
`1029`	`1029`	`BF->addDecorate(new SPIRVDecorateMaxConcurrencyINTEL(BF, Invocations));`
`1030`	`1030`	`}`
`1031`	`1031`	`}`
`1032`		`- if (MDNode *DisableLoopPipelining =`
`1033`		`- F->getMetadata(kSPIR2MD::DisableLoopPipelining)) {`
	`1032`	`+ if (MDNode *PipelineKernel = F->getMetadata(kSPIR2MD::PipelineKernel)) {`
`1034`	`1033`	`if (BM->isAllowedToUseExtension(`
`1035`	`1034`	`ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes)) {`
`1036`		`- size_t Disable = getMDOperandAsInt(DisableLoopPipelining, 0);`
`1037`		`- BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, !Disable));`
	`1035`	`+ size_t Pipeline = getMDOperandAsInt(PipelineKernel, 0);`
	`1036`	`+ BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, Pipeline));`
`1038`	`1037`	`}`
`1039`	`1038`	`}`
`1040`	`1039`