RISC-V simple CPU implementation

The CPU design implements a piplined RISC-V CPU consisting of 5 stages:

Stage One:

This stage is responsible for fetching the instruction of the instruction memory. It includes only the instruction memory component.

This stage is responsible for decoding the instruction and reading the registers data. It includes the control unit and the register file.

This stage will do the ALU calculation. It includes the ALU unit and the ALU control.

This stage will read or write to the RAM. It includes the RAM.

This stage will write back to the register file. and it's implemented in the same stage two file.

The CPU file connects all the previous stages together.