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Copy pathDWC_ETH_QOS_drv.c
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DWC_ETH_QOS_drv.c
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/* ============================================================================
* COPYRIGHT © 2015
*
* Toshiba America Electronic Components
*
* PROJECT: NEUTRINO
*
* Permission is hereby granted,
* free of charge, to any person obtaining a copy of this software annotated
* with this license and the Software, to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
*
* EXAMPLE PROGRAMS ARE PROVIDED AS-IS WITH NO WARRANTY OF ANY KIND,
* EITHER EXPRESS OR IMPLIED.
*
* TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
*
* THIS SOFTWARE IS PROVIDED AS-IS AND HAS NOT BEEN FULLY TESTED. IT IS
* INTENDED FOR REFERENCE USE ONLY.
*
* TOSHIBA DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES AND ALL LIABILITY OR
* ANY DAMAGES ASSOCIATED WITH YOUR USE OF THIS SOFTWARE.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY TOSHIBA SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL TOSHIBA BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* ========================================================================= */
/* =========================================================================
* The Synopsys DWC ETHER QOS Software Driver and documentation (hereinafter
* "Software") is an unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. Permission is hereby granted,
* free of charge, to any person obtaining a copy of this software annotated
* with this license and the Software, to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================= */
/*! History:
* 2-March-2016 : Initial
* 21-March-2016 : Added "DWC_ETH_QOS_config_phy_aneg" API and it's calls
*/
/*!@file: DWC_ETH_QOS_drv.c
* @brief: Driver functions.
*/
#include "DWC_ETH_QOS_yheader.h"
#include "DWC_ETH_QOS_yapphdr.h"
#include "DWC_ETH_QOS_drv.h"
extern ULONG dwc_eth_ntn_reg_pci_base_addr;
extern ULONG dwc_eth_ntn_SRAM_pci_base_addr_phy;
extern ULONG dwc_eth_ntn_SRAM_pci_base_addr_virt;
extern ULONG dwc_eth_ntn_hostmem_pci_base_addr_virt;
#include "DWC_ETH_QOS_yregacc.h"
static INT DWC_ETH_QOS_GStatus;
#ifdef NTN_POLLING_METHOD
static void* polling_task_data = NULL;
static struct delayed_work task;
#endif //NTN_POLLING_METHOD
/* SA(Source Address) operations on TX */
unsigned char mac_addr0[6] = { 0xE8, 0xE0, 0xB7, 0xB5, 0x7D, 0xF8 };
unsigned char mac_addr1[6] = { 0xE8, 0xE0, 0xB7, 0xB5, 0x7D, 0xF7 };
/* module parameters for configuring the queue modes
*
* */
static int q_op_mode[DWC_ETH_QOS_MAX_TX_QUEUE_CNT] = {
DWC_ETH_QOS_Q_GENERIC,
DWC_ETH_QOS_Q_AVB,
DWC_ETH_QOS_Q_AVB,
// DWC_ETH_QOS_Q_GENERIC,
// DWC_ETH_QOS_Q_GENERIC,
// DWC_ETH_QOS_Q_GENERIC,
// DWC_ETH_QOS_Q_GENERIC,
// DWC_ETH_QOS_Q_GENERIC
};
module_param_array(q_op_mode, int, NULL, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(q_op_mode,
"MTL queue operation mode [0-DISABLED, 1-AVB, 2-DCB, 3-GENERIC]");
#ifdef NTN_POLLING_METHOD
static void polling_task(void)
{
struct DWC_ETH_QOS_prv_data *pdata = (struct DWC_ETH_QOS_prv_data*)polling_task_data;
// unsigned int chInx;
DBGPR("-->polling_task");
if(pdata == NULL)
{
NMSGPR_ALERT( "polling_task data pointer is NULL");
return;
}
disable_irq(pdata->irq_number);
DWC_ETH_QOS_ISR_SW_DWC_ETH_QOS(pdata->irq_number, pdata);
enable_irq(pdata->irq_number);
DBGPR("<--polling_task");
schedule_delayed_work(&task, usecs_to_jiffies(NTN_POLL_DELAY_US));
return;
}
#endif //NTN_POLLING_METHOD
void DWC_ETH_QOS_stop_all_ch_tx_dma(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_stop_all_ch_tx_dma\n");
for(chInx = 0; chInx < NTN_TX_DMA_CH_CNT; chInx++){
if(!pdata->tx_dma_ch_for_host[chInx])
continue;
hw_if->stop_dma_tx(chInx);
}
DBGPR("<--DWC_ETH_QOS_stop_all_ch_tx_dma\n");
}
static void DWC_ETH_QOS_stop_all_ch_rx_dma(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_stop_all_ch_rx_dma\n");
for(chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++){
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
hw_if->stop_dma_rx(chInx);
}
DBGPR("<--DWC_ETH_QOS_stop_all_ch_rx_dma\n");
}
static void DWC_ETH_QOS_start_all_ch_tx_dma(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_start_all_ch_tx_dma\n");
for(chInx = 0; chInx < NTN_TX_DMA_CH_CNT; chInx++){
if(!pdata->tx_dma_ch_for_host[chInx])
continue;
hw_if->start_dma_tx(chInx);
}
DBGPR("<--DWC_ETH_QOS_start_all_ch_tx_dma\n");
}
static void DWC_ETH_QOS_start_all_ch_rx_dma(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_start_all_ch_rx_dma\n");
for(chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++){
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
hw_if->start_dma_rx(chInx);
}
DBGPR("<--DWC_ETH_QOS_start_all_ch_rx_dma\n");
}
static void DWC_ETH_QOS_napi_enable_mq(struct DWC_ETH_QOS_prv_data *pdata)
{
struct DWC_ETH_QOS_rx_dma_ch *rx_dma_ch = NULL;
int chInx;
DBGPR("-->DWC_ETH_QOS_napi_enable_mq\n");
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++) {
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
rx_dma_ch = GET_RX_DMA_CH_PTR(chInx);
napi_enable(&rx_dma_ch->napi);
}
DBGPR("<--DWC_ETH_QOS_napi_enable_mq\n");
}
static void DWC_ETH_QOS_all_ch_napi_disable(struct DWC_ETH_QOS_prv_data *pdata)
{
struct DWC_ETH_QOS_rx_dma_ch *rx_dma_ch = NULL;
int chInx;
DBGPR("-->DWC_ETH_QOS_napi_enable\n");
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++) {
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
rx_dma_ch = GET_RX_DMA_CH_PTR(chInx);
napi_disable(&rx_dma_ch->napi);
}
DBGPR("<--DWC_ETH_QOS_napi_enable\n");
}
/*!
* \details This function is invoked to stop device operation
* Following operations are performed in this function.
* - Stop the queue.
* - Stops DMA TX and RX.
* - Free the TX and RX skb's.
* - Issues soft reset to device.
*
* \param[in] pdata – pointer to private data structure.
*
* \return void
*/
static void DWC_ETH_QOS_stop_dev(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
struct desc_if_struct *desc_if = &(pdata->desc_if);
DBGPR("-->DWC_ETH_QOS_stop_dev\n");
netif_tx_disable(pdata->dev);
DWC_ETH_QOS_all_ch_napi_disable(pdata);
/* stop DMA TX/RX */
DWC_ETH_QOS_stop_all_ch_tx_dma(pdata);
DWC_ETH_QOS_stop_all_ch_rx_dma(pdata);
/* issue software reset to device */
hw_if->exit();
/* free tx skb's */
desc_if->tx_skb_free_mem(pdata, NTN_TX_DMA_CH_CNT);
/* free rx skb's */
desc_if->rx_skb_free_mem(pdata, NTN_RX_DMA_CH_CNT);
DBGPR("<--DWC_ETH_QOS_stop_dev\n");
}
static void DWC_ETH_QOS_tx_desc_mang_ds_dump(struct DWC_ETH_QOS_prv_data *pdata)
{
struct DWC_ETH_QOS_tx_wrapper_descriptor *tx_desc_data = NULL;
struct s_TX_NORMAL_DESC *tx_desc = NULL;
int chInx, i;
#ifndef YDEBUG
return;
#endif
NMSGPR_ALERT( "/**** TX DESC MANAGEMENT DATA STRUCTURE DUMP ****/\n");
NMSGPR_ALERT( "TX_DESC_QUEUE_CNT = %d\n", NTN_TX_DMA_CH_CNT);
for (chInx = 0; chInx < NTN_TX_DMA_CH_CNT; chInx++) {
if(!pdata->tx_dma_ch_for_host[chInx])
continue;
tx_desc_data = GET_TX_WRAPPER_DESC(chInx);
NMSGPR_ALERT( "DMA CHANNEL = %d\n", chInx);
NMSGPR_ALERT( "\tcur_tx = %d\n",
tx_desc_data->cur_tx);
NMSGPR_ALERT( "\tdirty_tx = %d\n",
tx_desc_data->dirty_tx);
NMSGPR_ALERT( "\tfree_desc_cnt = %d\n",
tx_desc_data->free_desc_cnt);
NMSGPR_ALERT( "\ttx_pkt_queued = %d\n",
tx_desc_data->tx_pkt_queued);
NMSGPR_ALERT( "\tqueue_stopped = %d\n",
tx_desc_data->queue_stopped);
NMSGPR_ALERT( "\tpacket_count = %d\n",
tx_desc_data->packet_count);
NMSGPR_ALERT( "\ttx_threshold_val = %d\n",
tx_desc_data->tx_threshold_val);
NMSGPR_ALERT( "\ttsf_on = %d\n",
tx_desc_data->tsf_on);
NMSGPR_ALERT( "\tosf_on = %d\n",
tx_desc_data->osf_on);
NMSGPR_ALERT( "\ttx_pbl = %d\n",
tx_desc_data->tx_pbl);
NMSGPR_ALERT( "\t[<desc_add> <index >] = <TDES0> : <TDES1> : <TDES2> : <TDES3>\n");
for (i = 0; i < TX_DESC_CNT; i++) {
tx_desc = GET_TX_DESC_PTR(chInx, i);
NMSGPR_ALERT( "\t[%4p %03d] = %#x : %#x : %#x : %#x\n",
tx_desc, i, tx_desc->TDES0, tx_desc->TDES1,
tx_desc->TDES2, tx_desc->TDES3);
}
}
NMSGPR_ALERT( "/************************************************/\n");
}
static void DWC_ETH_QOS_rx_desc_mang_ds_dump(struct DWC_ETH_QOS_prv_data *pdata)
{
struct DWC_ETH_QOS_rx_wrapper_descriptor *rx_desc_data = NULL;
struct s_RX_NORMAL_DESC *rx_desc = NULL;
int chInx, i;
#ifndef YDEBUG
return;
#endif
NMSGPR_ALERT( "/**** RX DESC MANAGEMENT DATA STRUCTURE DUMP ****/\n");
NMSGPR_ALERT( "RX_DESC_QUEUE_CNT = %d\n", NTN_RX_DMA_CH_CNT);
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++) {
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
rx_desc_data = GET_RX_WRAPPER_DESC(chInx);
NMSGPR_ALERT( "DMA CHANNEL = %d\n", chInx);
NMSGPR_ALERT( "\tcur_rx = %d\n",
rx_desc_data->cur_rx);
NMSGPR_ALERT( "\tdirty_rx = %d\n",
rx_desc_data->dirty_rx);
NMSGPR_ALERT( "\tpkt_received = %d\n",
rx_desc_data->pkt_received);
NMSGPR_ALERT( "\tskb_realloc_idx = %d\n",
rx_desc_data->skb_realloc_idx);
NMSGPR_ALERT( "\tskb_realloc_threshold = %d\n",
rx_desc_data->skb_realloc_threshold);
NMSGPR_ALERT( "\tuse_riwt = %d\n",
rx_desc_data->use_riwt);
NMSGPR_ALERT( "\trx_riwt = %d\n",
rx_desc_data->rx_riwt);
NMSGPR_ALERT( "\trx_coal_frames = %d\n",
rx_desc_data->rx_coal_frames);
NMSGPR_ALERT( "\trx_threshold_val = %d\n",
rx_desc_data->rx_threshold_val);
NMSGPR_ALERT( "\trsf_on = %d\n",
rx_desc_data->rsf_on);
NMSGPR_ALERT( "\trx_pbl = %d\n",
rx_desc_data->rx_pbl);
NMSGPR_ALERT( "\t[<desc_add> <index >] = <RDES0> : <RDES1> : <RDES2> : <RDES3>\n");
for (i = 0; i < RX_DESC_CNT; i++) {
rx_desc = GET_RX_DESC_PTR(chInx, i);
NMSGPR_ALERT( "\t[%4p %03d] = %#x : %#x : %#x : %#x\n",
rx_desc, i, rx_desc->RDES0, rx_desc->RDES1,
rx_desc->RDES2, rx_desc->RDES3);
}
}
NMSGPR_ALERT( "/************************************************/\n");
}
static void DWC_ETH_QOS_restart_phy(struct DWC_ETH_QOS_prv_data *pdata)
{
DBGPR("-->DWC_ETH_QOS_restart_phy\n");
pdata->oldlink = 0;
pdata->speed = 0;
pdata->oldduplex = -1;
if (pdata->phydev)
phy_start_aneg(pdata->phydev);
DBGPR("<--DWC_ETH_QOS_restart_phy\n");
}
/*!
* \details This function is invoked to start the device operation
* Following operations are performed in this function.
* - Initialize software states
* - Initialize the TX and RX descriptors queue.
* - Initialize the device to know state
* - Start the queue.
*
* \param[in] pdata – pointer to private data structure.
*
* \return void
*/
static void DWC_ETH_QOS_start_dev(struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
struct desc_if_struct *desc_if = &(pdata->desc_if);
DBGPR("-->DWC_ETH_QOS_start_dev\n");
/* reset all variables */
DWC_ETH_QOS_default_common_confs(pdata);
DWC_ETH_QOS_default_tx_confs(pdata);
DWC_ETH_QOS_default_rx_confs(pdata);
DWC_ETH_QOS_configure_rx_fun_ptr(pdata);
DWC_ETH_QOS_napi_enable_mq(pdata);
/* reinit descriptor */
desc_if->wrapper_tx_desc_init(pdata);
desc_if->wrapper_rx_desc_init(pdata);
DWC_ETH_QOS_tx_desc_mang_ds_dump(pdata);
DWC_ETH_QOS_rx_desc_mang_ds_dump(pdata);
/* initializes MAC and DMA */
hw_if->init(pdata);
if (pdata->vlan_hash_filtering)
hw_if->update_vlan_hash_table_reg(pdata->vlan_ht_or_id);
else
hw_if->update_vlan_id(pdata->vlan_ht_or_id);
DWC_ETH_QOS_restart_phy(pdata);
pdata->eee_enabled = DWC_ETH_QOS_eee_init(pdata);
netif_tx_wake_all_queues(pdata->dev);
DBGPR("<--DWC_ETH_QOS_start_dev\n");
}
/*!
* \details This function is invoked by isr handler when device issues an FATAL
* bus error interrupt. Following operations are performed in this function.
* - Stop the device.
* - Start the device
*
* \param[in] pdata – pointer to private data structure.
* \param[in] chInx – queue number.
*
* \return void
*/
static void DWC_ETH_QOS_restart_dev(struct DWC_ETH_QOS_prv_data *pdata,
UINT chInx)
{
struct desc_if_struct *desc_if = &(pdata->desc_if);
struct hw_if_struct *hw_if = &(pdata->hw_if);
struct DWC_ETH_QOS_rx_dma_ch *rx_dma_ch = GET_RX_DMA_CH_PTR(chInx);
DBGPR("-->DWC_ETH_QOS_restart_dev\n");
netif_stop_subqueue(pdata->dev, chInx);
napi_disable(&rx_dma_ch->napi);
/* stop DMA TX/RX */
hw_if->stop_dma_tx(chInx);
hw_if->stop_dma_rx(chInx);
/* free tx skb's */
desc_if->tx_skb_free_mem_single_q(pdata, chInx);
/* free rx skb's */
desc_if->rx_skb_free_mem_single_q(pdata, chInx);
if ((NTN_TX_QUEUE_CNT == 0) &&
(NTN_RX_QUEUE_CNT == 0)) {
/* issue software reset to device */
hw_if->exit();
DWC_ETH_QOS_configure_rx_fun_ptr(pdata);
DWC_ETH_QOS_default_common_confs(pdata);
}
/* reset all variables */
DWC_ETH_QOS_default_tx_confs_single_q(pdata, chInx);
DWC_ETH_QOS_default_rx_confs_single_q(pdata, chInx);
/* reinit descriptor */
desc_if->wrapper_tx_desc_init_single_q(pdata, chInx);
desc_if->wrapper_rx_desc_init_single_q(pdata, chInx);
napi_enable(&rx_dma_ch->napi);
/* initializes MAC and DMA
* NOTE : Do we need to init only one channel
* which generate FBE*/
hw_if->init(pdata);
DWC_ETH_QOS_restart_phy(pdata);
netif_wake_subqueue(pdata->dev, chInx);
DBGPR("<--DWC_ETH_QOS_restart_dev\n");
}
void DWC_ETH_QOS_disable_all_ch_rx_interrpt(
struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_disable_all_ch_rx_interrpt\n");
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++){
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
hw_if->disable_rx_interrupt(chInx);
}
DBGPR("<--DWC_ETH_QOS_disable_all_ch_rx_interrpt\n");
}
void DWC_ETH_QOS_enable_all_ch_rx_interrpt(
struct DWC_ETH_QOS_prv_data *pdata)
{
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx;
DBGPR("-->DWC_ETH_QOS_enable_all_ch_rx_interrpt\n");
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++){
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
hw_if->enable_rx_interrupt(chInx);
}
DBGPR("<--DWC_ETH_QOS_enable_all_ch_rx_interrpt\n");
}
/*!
* \brief Interrupt Service Routine
* \details Interrupt Service Routine
*
* \param[in] irq - interrupt number for particular device
* \param[in] device_id - pointer to device structure
* \return returns positive integer
* \retval IRQ_HANDLED
*/
irqreturn_t DWC_ETH_QOS_ISR_SW_DWC_ETH_QOS_DUMMY(int irq, void *device_id)
{
NDBGPR_L2("Dummy ISR called\n");
return IRQ_HANDLED;
}
#if 0
static void print_time2()
{
struct timespec now;
unsigned long long now_ns;
int diff;
static unsigned long long prev_ns = 0xFFFFFFFFFFFFFFFF;
getnstimeofday(&now);
now_ns = now.tv_sec;
now_ns = (now_ns*1000000000)+now.tv_nsec;
if(prev_ns == 0xFFFFFFFFFFFFFFFF)
prev_ns = now_ns;
diff = now_ns - prev_ns;
if(diff > 1000000) // ms
NMSGPR_INFO("ISR Entry Gap = %d\n", diff);
prev_ns = now_ns;
}
static void print_time(int val)
{
struct timespec now;
unsigned long long now_ns;
int diff;
static unsigned long long prev_ns = 0xFFFFFFFFFFFFFFFF;
getnstimeofday(&now);
now_ns = now.tv_sec;
now_ns = (now_ns*1000000000)+now.tv_nsec;
if(prev_ns == 0xFFFFFFFFFFFFFFFF)
prev_ns = now_ns;
if(val)
{
diff = now_ns - prev_ns;
if(diff > 500000) //
NMSGPR_INFO("ISR Execution time = %d\n", diff);
}
else{
prev_ns = now_ns;
//NMSGPR_INFO("first time : ");
}
}
#endif
irqreturn_t DWC_ETH_QOS_ISR_SW_DWC_ETH_QOS(int irq, void *device_id)
{
ULONG varNTN_INTC_INTSTATUS;
ULONG varNTN_INTC_MACSTATUS;
ULONG varNTN_INTC_INTMCUMASK1;
ULONG var_NTN_INTC_TDMSTATUS;
ULONG var_raw_DMA_RXCHSTS;
ULONG varDMA_RXCHSTS;
ULONG var_raw_DMA_TXCHSTS;
ULONG varDMA_TXCHSTS;
ULONG varDMA_RXCHINTMASK;
ULONG varDMA_TXCHINTMASK;
ULONG varBitField;
ULONG varMAC_ISR;
ULONG varMAC_IMR;
ULONG varMAC_PMTCSR;
struct DWC_ETH_QOS_prv_data *pdata =
(struct DWC_ETH_QOS_prv_data *)device_id;
struct net_device *dev = pdata->dev;
struct hw_if_struct *hw_if = &(pdata->hw_if);
UINT chInx, chSts;
ULONG temp;
int napi_sched = 0;
struct DWC_ETH_QOS_rx_dma_ch *rx_dma_ch = NULL;
ULONG varMAC_ANS = 0;
ULONG varMAC_PCS = 0;
DBGPR("-->DWC_ETH_QOS_ISR_SW_DWC_ETH_QOS\n");
/* Read interrupt mask */
NTN_INTC_INTMCUMASK1_RgRd(varNTN_INTC_INTMCUMASK1);
/* TOP level status register: Check if there is any interrupt from EMAC, if not return with IRQ_NONE. */
NTN_INTC_INTSTATUS_RgRd(varNTN_INTC_INTSTATUS);
if (GET_VALUE(varNTN_INTC_INTSTATUS, NTN_INTC_INTSTATUS_TXRX_LPOS, NTN_INTC_INTSTATUS_TXRX_HPOS))
{
NTN_INTC_MACSTATUS_RgRd(varNTN_INTC_MACSTATUS);
/* Handle DMA RX interrupts */
for (chInx = 0; chInx < NTN_RX_DMA_CH_CNT; chInx++) {
/* Check if Current DMA channel didn't raise an interrupt, continue to next channel */
if(!GET_VALUE(varNTN_INTC_MACSTATUS, (chInx+16), (chInx+16) ))
continue;
if(!pdata->rx_dma_ch_for_host[chInx])
continue;
rx_dma_ch = GET_RX_DMA_CH_PTR(chInx);
/* DMA RX Channel level status register */
DMA_RXCHSTS_RgRd(chInx, var_raw_DMA_RXCHSTS);
/* clear interrupts. This will clear INTC interrupt status as well. */
DMA_RXCHSTS_RgWr(chInx, var_raw_DMA_RXCHSTS);
NDBGPR_TS1("Raw DMA_RXCHSTS[%d] = %#lx\n", chInx, var_raw_DMA_RXCHSTS);
/* get enabled interrupt mask */
DMA_RXCHINTMASK_RgRd(chInx, varDMA_RXCHINTMASK);
varDMA_RXCHINTMASK &= DMA_RXCHINTMASK_MASK;
/* handle only those DMA interrupts which are enabled */
varDMA_RXCHSTS = (var_raw_DMA_RXCHSTS & varDMA_RXCHINTMASK);
NDBGPR_L2( "DMA_RXCHSTS[%d] = %#lx\n", chInx, varDMA_RXCHSTS);
if ((GET_VALUE(varDMA_RXCHSTS, DMA_RXCHSTS_RC_LPOS, DMA_RXCHSTS_RC_HPOS) & 1) ||
(GET_VALUE(varDMA_RXCHSTS, DMA_RXCHSTS_UNF_LPOS, DMA_RXCHSTS_UNF_HPOS) & 1)) {
if (!napi_sched) {
napi_sched = 1;
if (likely(napi_schedule_prep(&rx_dma_ch->napi))) {
DWC_ETH_QOS_disable_all_ch_rx_interrpt(pdata);
NDBGPR_TS2("Scheduling RX Poll\n");
__napi_schedule(&rx_dma_ch->napi);
} else {
DWC_ETH_QOS_disable_all_ch_rx_interrpt(pdata);
}
if ((GET_VALUE(varDMA_RXCHSTS, DMA_RXCHSTS_RC_LPOS, DMA_RXCHSTS_RC_HPOS) & 1))
pdata->xstats.rx_normal_irq_n[chInx]++;
else{
pdata->xstats.rx_buf_unavailable_irq_n[chInx]++;
NDBGPR_L2( "RX Buffer unavalialbe for Channel = %d\n", chInx);
}
}
}
if (GET_VALUE(varDMA_RXCHSTS, DMA_RXCHSTS_RS_LPOS, DMA_RXCHSTS_RS_HPOS) & 1) {
pdata->xstats.rx_process_stopped_irq_n[chInx]++;
NMSGPR_ALERT( "RX Stopped for Channel = %d\n", chInx);
DWC_ETH_QOS_GStatus = -E_DMA_RX_TS;
}
if (GET_VALUE(varDMA_RXCHSTS, DMA_RXCHSTS_FE_LPOS, DMA_RXCHSTS_FE_HPOS) & 1) {
pdata->xstats.fatal_bus_error_irq_n++;
DWC_ETH_QOS_GStatus = -E_DMA_RX_FE;
DMA_RXCHSTS_FESTS_UdfRd(chInx, varBitField);
NMSGPR_ALERT( "RX Fatal Bus error Status %#lx\n", varBitField);
DMA_RXCHSTS_CHSTS_UdfRd(chInx, varBitField);
NMSGPR_ALERT( "RX Channel Status %#lx\n", varBitField);
DWC_ETH_QOS_restart_dev(pdata, chInx);
}
chSts = GET_VALUE(var_raw_DMA_RXCHSTS, DMA_RXCHSTS_CHSTS_LPOS, DMA_RXCHSTS_CHSTS_HPOS);
switch(chSts)
{
case DMA_RXCHSTS_CHSTS_SUSPEND:
//NMSGPR_ALERT( "RX Channel %d Suspended\n", chInx);
break;
case DMA_RXCHSTS_CHSTS_STOP:
DMA_RXCHCTL_RgRd(chInx, temp);
NMSGPR_ALERT( "RX Channel %d Stopped : CTL = %lx\n", chInx, temp);
break;
}
}
/* Handle DMA TX interrupts */
for (chInx = 0; chInx < NTN_TX_DMA_CH_CNT; chInx++) {
/* Check if Current DMA channel didn't raise an interrupt, continue to next channel */
if(!GET_VALUE(varNTN_INTC_MACSTATUS, (chInx), (chInx) ))
continue;
if(!pdata->tx_dma_ch_for_host[chInx])
continue;
/* DMA TX Channel level status register */
DMA_TXCHSTS_RgRd(chInx, var_raw_DMA_TXCHSTS);
/* clear interrupts. This will clear INTC interrupt status as well. */
DMA_TXCHSTS_RgWr(chInx, var_raw_DMA_TXCHSTS);
NDBGPR_TS1("Raw DMA_TXCHSTS[%d] = %#lx\n", chInx, var_raw_DMA_TXCHSTS);
/* get enabled interrupt mask */
DMA_TXCHINTMASK_RgRd(chInx, varDMA_TXCHINTMASK);
varDMA_TXCHINTMASK &= DMA_TXCHINTMASK_MASK;
/* handle only those DMA interrupts which are enabled */
varDMA_TXCHSTS = (var_raw_DMA_TXCHSTS & varDMA_TXCHINTMASK);
NDBGPR_L2("DMA_TXCHSTS[%d] = %#lx\n", chInx, varDMA_TXCHSTS);
if (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_TC_LPOS, DMA_TXCHSTS_TC_HPOS) & 1) {
pdata->xstats.tx_normal_irq_n[chInx]++;
DWC_ETH_QOS_tx_interrupt(dev, pdata, chInx);
}
if (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_TS_LPOS, DMA_TXCHSTS_TS_HPOS) & 1) {
pdata->xstats.tx_process_stopped_irq_n[chInx]++;
NMSGPR_ALERT( "TX Stopped for Channel = %d\n", chInx);
DWC_ETH_QOS_GStatus = -E_DMA_TX_TS;
}
if (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_UNF_LPOS, DMA_TXCHSTS_UNF_HPOS) & 1) {
pdata->xstats.tx_buf_unavailable_irq_n[chInx]++;
DWC_ETH_QOS_GStatus = -E_DMA_TX_UNF;
if( (chInx == NTN_TX_PKT_AVB_CLASS_A) || (chInx == NTN_TX_PKT_AVB_CLASS_B) )
NDBGPR_L2( "TX Buffer underflow interrupt, It should be avoided for AVB traffic\n");
}
if (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_FE_LPOS, DMA_TXCHSTS_FE_HPOS) & 1) {
pdata->xstats.fatal_bus_error_irq_n++;
DWC_ETH_QOS_GStatus = -E_DMA_TX_FE;
DMA_TXCHSTS_FESTS_UdfRd(chInx, varBitField);
NMSGPR_ALERT( "TX Fatal Bus error Status %#lx\n", varBitField);
DMA_TXCHSTS_CHSTS_UdfRd(chInx, varBitField);
NMSGPR_ALERT( "TX Channel Status %#lx\n", varBitField);
DWC_ETH_QOS_restart_dev(pdata, chInx);
}
if ( (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_ETC_LPOS, DMA_TXCHSTS_ETC_HPOS) & 1) ){
NDBGPR_L2( "ETC Interrupt is not handled\n");
}
if ( (GET_VALUE(varDMA_TXCHSTS, DMA_TXCHSTS_CDE_LPOS, DMA_TXCHSTS_CDE_HPOS) & 1) ){
NMSGPR_ALERT( "CDE Interrupt is not handled\n");
}
chSts = GET_VALUE(var_raw_DMA_TXCHSTS, DMA_TXCHSTS_CHSTS_LPOS, DMA_TXCHSTS_CHSTS_HPOS);
switch(chSts)
{
case DMA_TXCHSTS_CHSTS_SUSPEND:
//NMSGPR_ALERT( "TX Channel %d Suspended\n", chInx);
break;
case DMA_TXCHSTS_CHSTS_STOP:
NMSGPR_ALERT( "TX Channel %d Stopped\n", chInx);
break;
}
}
}
/* Handle MAC interrupts */
if (GET_VALUE(varNTN_INTC_INTSTATUS, NTN_INTC_INTSTATUS_MAC_LPOS, NTN_INTC_INTSTATUS_MAC_HPOS)) {
MAC_ISR_RgRd(varMAC_ISR);
NDBGPR_L2("MAC_ISR = %#lx\n", varMAC_ISR);
/* handle only those MAC interrupts which are enabled */
MAC_IMR_RgRd(varMAC_IMR);
varMAC_ISR = (varMAC_ISR & varMAC_IMR);
/* PMT interrupt */
if (GET_VALUE(varMAC_ISR, MAC_ISR_PMTIS_LPOS, MAC_ISR_PMTIS_HPOS) & 1) {
pdata->xstats.pmt_irq_n++;
DWC_ETH_QOS_GStatus = S_MAC_ISR_PMTIS;
MAC_PMTCSR_RgRd(varMAC_PMTCSR);
if (pdata->power_down)
DWC_ETH_QOS_powerup(pdata->dev, DWC_ETH_QOS_IOCTL_CONTEXT);
}
/* RGMII/SMII interrupt */
if (GET_VALUE(varMAC_ISR, MAC_ISR_RGSMIIS_LPOS, MAC_ISR_RGSMIIS_HPOS) & 1) {
MAC_PCS_RgRd(varMAC_PCS);
NMSGPR_ALERT( "RGMII/SMII interrupt: MAC_PCS = %#lx\n", varMAC_PCS);
if ((varMAC_PCS & 0x80000) == 0x80000) {
pdata->pcs_link = 1;
netif_carrier_on(dev);
if ((varMAC_PCS & 0x10000) == 0x10000) {
pdata->pcs_duplex = 1;
hw_if->set_full_duplex();
} else {
pdata->pcs_duplex = 0;
hw_if->set_half_duplex();
}
if ((varMAC_PCS & 0x60000) == 0x0) {
pdata->pcs_speed = SPEED_10;
hw_if->set_mii_speed_10();
} else if ((varMAC_PCS & 0x60000) == 0x20000) {
pdata->pcs_speed = SPEED_100;
hw_if->set_mii_speed_100();
} else if ((varMAC_PCS & 0x60000) == 0x40000) {
pdata->pcs_speed = SPEED_1000;
hw_if->set_gmii_speed();
}
NMSGPR_ALERT( "Link is UP:%dMbps & %s duplex\n",
pdata->pcs_speed, pdata->pcs_duplex ? "Full" : "Half");
} else {
NMSGPR_ALERT( "Link is Down\n");
pdata->pcs_link = 0;
netif_carrier_off(dev);
}
}
/* PCS Link Status interrupt */
if (GET_VALUE(varMAC_ISR, MAC_ISR_PCSLCHGIS_LPOS, MAC_ISR_PCSLCHGIS_HPOS) & 1) {
NMSGPR_ALERT( "PCS Link Status interrupt\n");
MAC_ANS_RgRd(varMAC_ANS);
if (GET_VALUE(varMAC_ANS, MAC_ANS_LS_LPOS, MAC_ANS_LS_HPOS) & 1) {
NMSGPR_ALERT( "Link: Up\n");
netif_carrier_on(dev);
pdata->pcs_link = 1;
} else {
NMSGPR_ALERT( "Link: Down\n");
netif_carrier_off(dev);
pdata->pcs_link = 0;
}
}
/* PCS Auto-Negotiation Complete interrupt */
if (GET_VALUE(varMAC_ISR, MAC_ISR_PCSANCIS_LPOS, MAC_ISR_PCSANCIS_HPOS) & 1) {
NMSGPR_ALERT( "PCS Auto-Negotiation Complete interrupt\n");
MAC_ANS_RgRd(varMAC_ANS);
}
/* EEE interrupts */
if (GET_VALUE(varMAC_ISR, MAC_ISR_LPI_LPOS, MAC_ISR_LPI_HPOS) & 1) {
DWC_ETH_QOS_handle_eee_interrupt(pdata);
}
}
/* Handle MAC LPI interrupts */
if (GET_VALUE(varNTN_INTC_INTSTATUS, NTN_INTC_INTSTATUS_MAC_LPI_LPOS, NTN_INTC_INTSTATUS_MAC_LPI_HPOS)) {
NMSGPR_ALERT( "Neutrino INTC MAC LPI status bit is set.\n");
}
/* Handle MAC PM interrupts */
if (GET_VALUE(varNTN_INTC_INTSTATUS, NTN_INTC_INTSTATUS_MAC_PM_LPOS, NTN_INTC_INTSTATUS_MAC_PM_HPOS)) {
NMSGPR_ALERT( "Neutrino INTC MAC PM status bit is set.\n");
}
/* Handle TDM interrupts */
if (GET_VALUE(varNTN_INTC_INTSTATUS, NTN_INTC_INTSTATUS_TDM_LPOS, NTN_INTC_INTSTATUS_TDM_HPOS)) {
NTN_INTC_TDMSTATUS_RgRd(var_NTN_INTC_TDMSTATUS);
NTN_INTC_TDMSTATUS_RgWr(var_NTN_INTC_TDMSTATUS);
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_IP_0_OVERFLOW){
NMSGPR_ALERT( "Neutrino TDM Input 0 Overflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_IP_1_OVERFLOW){
NMSGPR_ALERT( "Neutrino TDM Input 1 Overflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_IP_2_OVERFLOW){
NMSGPR_ALERT( "Neutrino TDM Input 2 Overflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_IP_3_OVERFLOW){
NMSGPR_ALERT( "Neutrino TDM Input 3 Overflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_OP_OVERFLOW){
NMSGPR_ALERT( "Neutrino TDM Output Overflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_OP_UNDERFLOW){
NMSGPR_ALERT( "Neutrino TDM Output Underflow detected.\n");
}
if(var_NTN_INTC_TDMSTATUS & NTN_INTC_TDM_GENERAL_ERROR){
NMSGPR_ALERT( "Neutrino TDM General error detected.\n");
}
}
/* Enable interrupts again : Only TX & RX DMA channel interrupts */
varNTN_INTC_INTMCUMASK1 &= NTN_INTC_GMAC_INT_MASK;
NTN_INTC_INTMCUMASK1_RgWr(varNTN_INTC_INTMCUMASK1);
DBGPR("<--DWC_ETH_QOS_ISR_SW_DWC_ETH_QOS\n");
return IRQ_HANDLED;
}
/*!
* \brief API to get all hw features.
*
* \details This function is used to check what are all the different
* features the device supports.
*
* \param[in] pdata - pointer to driver private structure
*
* \return none
*/
void DWC_ETH_QOS_get_all_hw_features(struct DWC_ETH_QOS_prv_data *pdata)
{
unsigned int varMAC_HFR0;
unsigned int varMAC_HFR1;
unsigned int varMAC_HFR2;
DBGPR("-->DWC_ETH_QOS_get_all_hw_features\n");
MAC_HFR0_RgRd(varMAC_HFR0);
MAC_HFR1_RgRd(varMAC_HFR1);
MAC_HFR2_RgRd(varMAC_HFR2);
memset(&pdata->hw_feat, 0, sizeof(pdata->hw_feat));
pdata->hw_feat.mii_sel = ((varMAC_HFR0 >> 0) & MAC_HFR0_MIISEL_Mask);
pdata->hw_feat.gmii_sel = ((varMAC_HFR0 >> 1) & MAC_HFR0_GMIISEL_Mask);
pdata->hw_feat.hd_sel = ((varMAC_HFR0 >> 2) & MAC_HFR0_HDSEL_Mask);
pdata->hw_feat.pcs_sel = ((varMAC_HFR0 >> 3) & MAC_HFR0_PCSSEL_Mask);
pdata->hw_feat.vlan_hash_en =
((varMAC_HFR0 >> 4) & MAC_HFR0_VLANHASEL_Mask);
pdata->hw_feat.sma_sel = ((varMAC_HFR0 >> 5) & MAC_HFR0_SMASEL_Mask);
pdata->hw_feat.rwk_sel = ((varMAC_HFR0 >> 6) & MAC_HFR0_RWKSEL_Mask);
pdata->hw_feat.mgk_sel = ((varMAC_HFR0 >> 7) & MAC_HFR0_MGKSEL_Mask);
pdata->hw_feat.mmc_sel = ((varMAC_HFR0 >> 8) & MAC_HFR0_MMCSEL_Mask);
pdata->hw_feat.arp_offld_en =
((varMAC_HFR0 >> 9) & MAC_HFR0_ARPOFFLDEN_Mask);
pdata->hw_feat.ts_sel =
((varMAC_HFR0 >> 12) & MAC_HFR0_TSSSEL_Mask);
pdata->hw_feat.eee_sel = ((varMAC_HFR0 >> 13) & MAC_HFR0_EEESEL_Mask);
pdata->hw_feat.tx_coe_sel =
((varMAC_HFR0 >> 14) & MAC_HFR0_TXCOESEL_Mask);
pdata->hw_feat.rx_coe_sel =
((varMAC_HFR0 >> 16) & MAC_HFR0_RXCOE_Mask);
pdata->hw_feat.mac_addr16_sel =
((varMAC_HFR0 >> 18) & MAC_HFR0_ADDMACADRSEL_Mask);
pdata->hw_feat.mac_addr32_sel =
((varMAC_HFR0 >> 23) & MAC_HFR0_MACADR32SEL_Mask);
pdata->hw_feat.mac_addr64_sel =
((varMAC_HFR0 >> 24) & MAC_HFR0_MACADR64SEL_Mask);
pdata->hw_feat.tsstssel =
((varMAC_HFR0 >> 25) & MAC_HFR0_TSINTSEL_Mask);
pdata->hw_feat.sa_vlan_ins =
((varMAC_HFR0 >> 27) & MAC_HFR0_SAVLANINS_Mask);
pdata->hw_feat.act_phy_sel =
((varMAC_HFR0 >> 28) & MAC_HFR0_ACTPHYSEL_Mask);