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mv_ddr4_training_calibration.c
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mv_ddr4_training_calibration.c
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/*******************************************************************************
Copyright (C) 2016 Marvell International Ltd.
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the three
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
This program is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation, either version 2 of the License, or any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
********************************************************************************
Marvell GNU General Public License FreeRTOS Exception
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the Lesser
General Public License Version 2.1 plus the following FreeRTOS exception.
An independent module is a module which is not derived from or based on
FreeRTOS.
Clause 1:
Linking FreeRTOS statically or dynamically with other modules is making a
combined work based on FreeRTOS. Thus, the terms and conditions of the GNU
General Public License cover the whole combination.
As a special exception, the copyright holder of FreeRTOS gives you permission
to link FreeRTOS with independent modules that communicate with FreeRTOS solely
through the FreeRTOS API interface, regardless of the license terms of these
independent modules, and to copy and distribute the resulting combined work
under terms of your choice, provided that:
1. Every copy of the combined work is accompanied by a written statement that
details to the recipient the version of FreeRTOS used and an offer by yourself
to provide the FreeRTOS source code (including any modifications you may have
made) should the recipient request it.
2. The combined work is not itself an RTOS, scheduler, kernel or related
product.
3. The independent modules add significant and primary functionality to
FreeRTOS and do not merely extend the existing functionality already present in
FreeRTOS.
Clause 2:
FreeRTOS may not be used for any competitive or comparative purpose, including
the publication of any form of run time or compile time metric, without the
express permission of Real Time Engineers Ltd. (this is the norm within the
industry and is intended to ensure information accuracy).
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#if defined(CONFIG_DDR4)
/* DESCRIPTION: DDR4 Receiver and DQVref Calibration */
#include "ddr3_init.h"
#include "mv_ddr4_training_calibration.h"
#include "mv_ddr4_training.h"
#include "mv_ddr4_mpr_pda_if.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#define RX_DIR 0
#define TX_DIR 1
#define MAX_DIR_TYPES 2
#define RECEIVER_DC_STEP_SIZE 3
#define RECEIVER_DC_MIN_RANGE 0
#define RECEIVER_DC_MAX_RANGE 63
#define RECEIVER_DC_MAX_COUNT (((RECEIVER_DC_MAX_RANGE - RECEIVER_DC_MIN_RANGE) / RECEIVER_DC_STEP_SIZE) + 1)
#define PBS_VAL_FACTOR 1000
#define MV_DDR_VW_TX_NOISE_FILTER 8 /* adlls */
u8 dq_vref_vec[MAX_BUS_NUM]; /* stability support */
u8 rx_eye_hi_lvl[MAX_BUS_NUM]; /* rx adjust support */
u8 rx_eye_lo_lvl[MAX_BUS_NUM]; /* rx adjust support */
static u8 pbs_max = 31;
static u8 vdq_tv; /* vref value for dq vref calibration */
static u8 duty_cycle; /* duty cycle value for receiver calibration */
static u8 rx_vw_pos[MAX_INTERFACE_NUM][MAX_BUS_NUM];
static u8 patterns_byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM];
static const char *str_dir[MAX_DIR_TYPES] = {"read", "write"};
static u8 center_low_element_get(u8 dir, u8 pbs_element, u16 lambda, u8 pbs_max_val)
{
u8 result;
if (dir == RX_DIR)
result = pbs_element * lambda / PBS_VAL_FACTOR;
else
result = (pbs_max_val - pbs_element) * lambda / PBS_VAL_FACTOR;
return result;
}
static u8 center_high_element_get(u8 dir, u8 pbs_element, u16 lambda, u8 pbs_max_val)
{
u8 result;
if (dir == RX_DIR)
result = (pbs_max_val - pbs_element) * lambda / PBS_VAL_FACTOR;
else
result = pbs_element * lambda / PBS_VAL_FACTOR;
return result;
}
static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*copt)[MAX_BUS_NUM],
u8 (*pbs_result)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*vw_size)[MAX_BUS_NUM],
u8 mode, u16 param0, u8 param1);
static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs);
static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_result, u8 *copt);
static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v,
u8 vw_num, u8 *v_opt, u8 *t_opt);
static int mv_ddr4_tap_tuning(u8 dev_num, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 mode);
/* dq vref calibration flow */
int mv_ddr4_dq_vref_calibration(u8 dev_num, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS])
{
u32 if_id, subphy_num;
u32 vref_idx, dq_idx, pad_num = 0;
u8 dq_vref_start_win[MAX_INTERFACE_NUM][MAX_BUS_NUM][MV_DDR4_VREF_MAX_COUNT];
u8 dq_vref_end_win[MAX_INTERFACE_NUM][MAX_BUS_NUM][MV_DDR4_VREF_MAX_COUNT];
u8 valid_win_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 c_opt_per_bus[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 valid_vref_cnt[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 valid_vref_ptr[MAX_INTERFACE_NUM][MAX_BUS_NUM][MV_DDR4_VREF_MAX_COUNT];
u8 center_adll[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 center_vref[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 pbs_res_per_bus[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
u16 vref_avg, vref_subphy_num;
int vref_tap_idx;
int vref_range_min;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum mv_ddr4_vref_subphy_cal_state all_subphys_state = MV_DDR4_VREF_SUBPHY_CAL_ABOVE;
int tap_tune_passed = 0;
enum mv_ddr4_vref_tap_state vref_tap_set_state = MV_DDR4_VREF_TAP_START;
enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
u8 subphy_max = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
enum mv_ddr4_vref_subphy_cal_state vref_state_per_subphy[MAX_INTERFACE_NUM][MAX_BUS_NUM];
int status;
static u8 vref_byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM][MV_DDR4_VREF_MAX_RANGE];
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO, ("Starting ddr4 dq vref calibration training stage\n"));
vdq_tv = 0;
duty_cycle = 0;
/* reset valid vref counter per if and subphy */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
for (subphy_num = 0; subphy_num < MAX_BUS_NUM; subphy_num++) {
valid_vref_cnt[if_id][subphy_num] = 0;
vref_state_per_subphy[if_id][subphy_num] = MV_DDR4_VREF_SUBPHY_CAL_ABOVE;
}
}
if (mv_ddr4_tap_tuning(dev_num, pbs_tap_factor, TX_DIR) == MV_OK)
tap_tune_passed = 1;
/* place dram to vref training mode */
mv_ddr4_vref_training_mode_ctrl(dev_num, 0, ACCESS_TYPE_MULTICAST, 1);
/* main loop for 2d scan (low_to_high voltage scan) */
vref_tap_idx = MV_DDR4_VREF_MAX_RANGE;
vref_range_min = MV_DDR4_VREF_MIN_RANGE;
if (vref_range_min < MV_DDR4_VREF_STEP_SIZE)
vref_range_min = MV_DDR4_VREF_STEP_SIZE;
/* clean vref status array */
memset(vref_byte_status, BYTE_NOT_DEFINED, sizeof(vref_byte_status));
for (vref_tap_idx = MV_DDR4_VREF_MAX_RANGE; (vref_tap_idx >= vref_range_min) &&
(all_subphys_state != MV_DDR4_VREF_SUBPHY_CAL_UNDER);
vref_tap_idx -= MV_DDR4_VREF_STEP_SIZE) {
/* set new vref training value in dram */
mv_ddr4_vref_tap_set(dev_num, 0, ACCESS_TYPE_MULTICAST, vref_tap_idx, vref_tap_set_state);
if (tap_tune_passed == 0) {
if (mv_ddr4_tap_tuning(dev_num, pbs_tap_factor, TX_DIR) == MV_OK)
tap_tune_passed = 1;
else
continue;
}
if (mv_ddr4_centralization(dev_num, pbs_tap_factor, c_opt_per_bus, pbs_res_per_bus,
valid_win_size, TX_DIR, vref_tap_idx, 0) != MV_OK) {
DEBUG_CALIBRATION(DEBUG_LEVEL_ERROR,
("error: %s: ddr4 centralization failed (dq vref tap index %d)!!!\n",
__func__, vref_tap_idx));
continue;
}
/* go over all results and find out the vref start and end window */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
if (valid_win_size[if_id][subphy_num] > MV_DDR_VW_TX_NOISE_FILTER) {
if (vref_state_per_subphy[if_id][subphy_num] == MV_DDR4_VREF_SUBPHY_CAL_UNDER)
DEBUG_CALIBRATION(DEBUG_LEVEL_ERROR,
("warning: %s: subphy %d vref tap %d voltage noise\n",
__func__, subphy_num, vref_tap_idx));
/* window is valid; keep current vref_tap_idx value and increment counter */
vref_idx = valid_vref_cnt[if_id][subphy_num];
valid_vref_ptr[if_id][subphy_num][vref_idx] = vref_tap_idx;
valid_vref_cnt[if_id][subphy_num]++;
/* set 0 for possible negative values */
vref_byte_status[if_id][subphy_num][vref_idx] |=
patterns_byte_status[if_id][subphy_num];
dq_vref_start_win[if_id][subphy_num][vref_idx] =
c_opt_per_bus[if_id][subphy_num] + 1 -
valid_win_size[if_id][subphy_num] / 2;
dq_vref_start_win[if_id][subphy_num][vref_idx] =
(valid_win_size[if_id][subphy_num] % 2 == 0) ?
dq_vref_start_win[if_id][subphy_num][vref_idx] :
dq_vref_start_win[if_id][subphy_num][vref_idx] - 1;
dq_vref_end_win[if_id][subphy_num][vref_idx] =
c_opt_per_bus[if_id][subphy_num] +
valid_win_size[if_id][subphy_num] / 2;
vref_state_per_subphy[if_id][subphy_num] = MV_DDR4_VREF_SUBPHY_CAL_INSIDE;
} else if (vref_state_per_subphy[if_id][subphy_num] == MV_DDR4_VREF_SUBPHY_CAL_INSIDE) {
vref_state_per_subphy[if_id][subphy_num] = MV_DDR4_VREF_SUBPHY_CAL_UNDER;
}
} /* subphy */
} /* if */
/* check all subphys are in under state */
all_subphys_state = MV_DDR4_VREF_SUBPHY_CAL_UNDER;
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
if (vref_state_per_subphy[if_id][subphy_num] != MV_DDR4_VREF_SUBPHY_CAL_UNDER)
all_subphys_state = MV_DDR4_VREF_SUBPHY_CAL_INSIDE;
}
}
}
if (tap_tune_passed == 0) {
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO,
("%s: tap tune not passed on any dq_vref value\n", __func__));
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* report fail for all active interfaces; multi-interface support - tbd */
flow_result[if_id] = TEST_FAILED;
}
return MV_FAIL;
}
/* close vref range */
mv_ddr4_vref_tap_set(dev_num, 0, ACCESS_TYPE_MULTICAST, vref_tap_idx, MV_DDR4_VREF_TAP_END);
/*
* find out the results with the mixed and low states and move the low state 64 adlls in case
* the center of the ui is smaller than 31
*/
for (vref_idx = 0; vref_idx < MV_DDR4_VREF_MAX_RANGE; vref_idx++) {
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
if (((vref_byte_status[if_id][subphy_num][vref_idx]) &
(BYTE_HOMOGENEOUS_LOW | BYTE_SPLIT_OUT_MIX)) ==
(BYTE_HOMOGENEOUS_LOW | BYTE_SPLIT_OUT_MIX)) {
if ((dq_vref_start_win[if_id][subphy_num][vref_idx] +
dq_vref_end_win[if_id][subphy_num][vref_idx]) / 2 <= 31) {
dq_vref_start_win[if_id][subphy_num][vref_idx] += 64;
dq_vref_end_win[if_id][subphy_num][vref_idx] += 64;
DEBUG_CALIBRATION
(DEBUG_LEVEL_TRACE,
("%s vref_idx %d if %d subphy %d added 64 adlls to window\n",
__func__, valid_vref_ptr[if_id][subphy_num][vref_idx],
if_id, subphy_num));
}
}
}
}
}
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO,
("calculating center of mass for subphy %d, valid window size %d\n",
subphy_num, valid_win_size[if_id][subphy_num]));
if (valid_vref_cnt[if_id][subphy_num] > 0) {
/* calculate center of mass sampling point (t, v) for each subphy */
status = mv_ddr4_center_of_mass_calc(dev_num, if_id, subphy_num, TX_DIR,
dq_vref_start_win[if_id][subphy_num],
dq_vref_end_win[if_id][subphy_num],
valid_vref_ptr[if_id][subphy_num],
valid_vref_cnt[if_id][subphy_num],
¢er_vref[if_id][subphy_num],
¢er_adll[if_id][subphy_num]);
if (status != MV_OK)
return status;
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO,
("center of mass results: vref %d, adll %d\n",
center_vref[if_id][subphy_num], center_adll[if_id][subphy_num]));
} else {
DEBUG_CALIBRATION(DEBUG_LEVEL_ERROR,
("%s subphy %d no vref results to calculate the center of mass\n",
__func__, subphy_num));
status = MV_ERROR;
return status;
}
}
}
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
vref_avg = 0;
vref_subphy_num = 0;
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
vref_avg += center_vref[if_id][subphy_num];
dq_vref_vec[subphy_num] = center_vref[if_id][subphy_num];
vref_subphy_num++;
}
mv_ddr4_vref_tap_set(dev_num, if_id, ACCESS_TYPE_UNICAST,
vref_avg / vref_subphy_num, MV_DDR4_VREF_TAP_START);
mv_ddr4_vref_tap_set(dev_num, if_id, ACCESS_TYPE_UNICAST,
vref_avg / vref_subphy_num, MV_DDR4_VREF_TAP_END);
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO, ("final vref average %d\n", vref_avg / vref_subphy_num));
/* run centralization again with optimal vref to update global structures */
mv_ddr4_centralization(dev_num, pbs_tap_factor, c_opt_per_bus, pbs_res_per_bus, valid_win_size,
TX_DIR, vref_avg / vref_subphy_num, duty_cycle);
}
/* return dram from vref DRAM from vref training mode */
mv_ddr4_vref_training_mode_ctrl(dev_num, 0, ACCESS_TYPE_MULTICAST, 0);
/* dqs tx reposition calculation */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
pad_num = dq_map_table[dq_idx +
subphy_num * BUS_WIDTH_IN_BITS +
if_id * BUS_WIDTH_IN_BITS * subphy_max];
status = ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, ACCESS_TYPE_UNICAST,
subphy_num, DDR_PHY_DATA,
0x10 + pad_num + effective_cs * 0x10,
pbs_res_per_bus[if_id][subphy_num][dq_idx]);
if (status != MV_OK)
return status;
}
status = ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, ACCESS_TYPE_UNICAST,
subphy_num, DDR_PHY_DATA,
CTX_PHY_REG(effective_cs),
center_adll[if_id][subphy_num] % 64);
if (status != MV_OK)
return status;
}
}
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* report pass for all active interfaces; multi-interface support - tbd */
flow_result[if_id] = TEST_SUCCESS;
}
return MV_OK;
}
/* centralization flow */
static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*copt)[MAX_BUS_NUM],
u8 (*pbs_result)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*vw_size)[MAX_BUS_NUM],
u8 mode, u16 param0, u8 param1)
{
/* FIXME: remove the dependency in 64bit */
#if defined(CONFIG_64BIT)
#define MV_DDR_NUM_OF_CENTRAL_PATTERNS (PATTERN_KILLER_DQ7_64 - PATTERN_KILLER_DQ0 + 1)
#else
#define MV_DDR_NUM_OF_CENTRAL_PATTERNS (PATTERN_KILLER_DQ7 - PATTERN_KILLER_DQ0 + 1)
#endif
static u8 subphy_end_win[MAX_DIR_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
static u8 subphy_start_win[MAX_DIR_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
static u8 final_start_win[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
static u8 final_end_win[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
u32 if_id, subphy_num, pattern_id, pattern_loop_idx, bit_num;
u8 curr_start_win[BUS_WIDTH_IN_BITS];
u8 curr_end_win[BUS_WIDTH_IN_BITS];
static u8 start_win_db[MV_DDR_NUM_OF_CENTRAL_PATTERNS][MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
static u8 end_win_db[MV_DDR_NUM_OF_CENTRAL_PATTERNS][MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
u8 curr_win[BUS_WIDTH_IN_BITS];
u8 opt_win, waste_win, start_win_skew, end_win_skew;
u8 final_subphy_win[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
enum hws_training_result result_type = RESULT_PER_BIT;
enum hws_dir direction;
enum hws_search_dir search_dir;
u32 *result[HWS_SEARCH_DIR_LIMIT];
u32 max_win_size;
u8 curr_end_win_min, curr_start_win_max;
u32 cs_ena_reg_val[MAX_INTERFACE_NUM];
u8 current_byte_status;
int status;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
u8 subphy_max = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* save current cs enable reg val */
status = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG,
cs_ena_reg_val, MASK_ALL_BITS);
if (status != MV_OK)
return status;
/* enable single cs */
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG,
(0x1 << 3), (0x1 << 3));
if (status != MV_OK)
return status;
}
if (mode == TX_DIR) {
max_win_size = MAX_WINDOW_SIZE_TX;
direction = OPER_WRITE;
} else {
max_win_size = MAX_WINDOW_SIZE_RX;
direction = OPER_READ;
}
/* database initialization */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
patterns_byte_status[if_id][subphy_num] = BYTE_NOT_DEFINED;
subphy_end_win[mode][if_id][subphy_num] = (max_win_size - 1);
subphy_start_win[mode][if_id][subphy_num] = 0;
vw_size[if_id][subphy_num] = (max_win_size - 1);
for (bit_num = 0; bit_num < BUS_WIDTH_IN_BITS; bit_num++) {
final_start_win[if_id][subphy_num][bit_num] = 0;
final_end_win[if_id][subphy_num][bit_num] = (max_win_size - 1);
if (mode == TX_DIR)
final_end_win[if_id][subphy_num][bit_num] = (2 * max_win_size - 1);
}
if (mode == TX_DIR) {
subphy_end_win[mode][if_id][subphy_num] = (2 * max_win_size - 1);
vw_size[if_id][subphy_num] = (2 * max_win_size - 1);
}
}
}
/* main flow */
/* FIXME: hard-coded "22" below for PATTERN_KILLER_DQ7_64 enum hws_pattern */
for (pattern_id = PATTERN_KILLER_DQ0, pattern_loop_idx = 0;
pattern_id <= (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) ? 22 : PATTERN_KILLER_DQ7);
pattern_id++, pattern_loop_idx++) {
ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, result_type, HWS_CONTROL_ELEMENT_ADLL,
PARAM_NOT_CARE, direction, tm->if_act_mask,
0x0, max_win_size - 1, max_win_size - 1, pattern_id,
EDGE_FPF, CS_SINGLE, PARAM_NOT_CARE, training_result);
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
/*
* in case the previous patterns found the current subphy as BYTE_NOT_DEFINED,
* continue to next subphy
*/
if ((patterns_byte_status[if_id][subphy_num] == BYTE_NOT_DEFINED) &&
(pattern_id != PATTERN_KILLER_DQ0))
continue;
/*
* in case the result of the current subphy is BYTE_NOT_DEFINED mark the
* pattern byte status as BYTE_NOT_DEFINED
*/
current_byte_status = mv_ddr_tip_sub_phy_byte_status_get(if_id, subphy_num);
if (current_byte_status == BYTE_NOT_DEFINED) {
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_INFO,
("%s:%s: failed to lock subphy, pat %d if %d subphy %d\n",
__func__, str_dir[mode], pattern_id, if_id, subphy_num));
patterns_byte_status[if_id][subphy_num] = BYTE_NOT_DEFINED;
/* update the valid window size which is return value from this function */
vw_size[if_id][subphy_num] = 0;
/* continue to next subphy */
continue;
}
/* set the status of this byte */
patterns_byte_status[if_id][subphy_num] |= current_byte_status;
for (search_dir = HWS_LOW2HIGH; search_dir <= HWS_HIGH2LOW; search_dir++) {
status = ddr3_tip_read_training_result(dev_num, if_id, ACCESS_TYPE_UNICAST,
subphy_num, ALL_BITS_PER_PUP,
search_dir, direction, result_type,
TRAINING_LOAD_OPERATION_UNLOAD,
CS_SINGLE, &result[search_dir],
1, 0, 0);
if (status != MV_OK)
return status;
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_INFO,
("param0 %d param1 %d pat %d if %d subphy %d "
"regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
param0, param1, pattern_id, if_id, subphy_num,
result[search_dir][0], result[search_dir][1],
result[search_dir][2], result[search_dir][3],
result[search_dir][4], result[search_dir][5],
result[search_dir][6], result[search_dir][7]));
}
for (bit_num = 0; bit_num < BUS_WIDTH_IN_BITS; bit_num++) {
/* read result success */
DEBUG_DDR4_CENTRALIZATION(
DEBUG_LEVEL_INFO,
("%s %s subphy locked, pat %d if %d subphy %d\n",
__func__, str_dir[mode], pattern_id,
if_id, subphy_num));
start_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] =
GET_TAP_RESULT(result[HWS_LOW2HIGH][bit_num], EDGE_1);
end_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] =
GET_TAP_RESULT(result[HWS_HIGH2LOW][bit_num], EDGE_1);
}
} /* subphy */
} /* interface */
} /* pattern */
/*
* check if the current patterns subphys in all interfaces has mixed and low byte states
* in that case add 64 adlls to the low byte
*/
for (pattern_id = PATTERN_KILLER_DQ0, pattern_loop_idx = 0;
pattern_id <= (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) ? 22 : PATTERN_KILLER_DQ7);
pattern_id++, pattern_loop_idx++) {
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
if (patterns_byte_status[if_id][subphy_num] == BYTE_NOT_DEFINED)
continue;
opt_win = 2 * max_win_size; /* initialize opt_win */
/* in case this byte in the pattern is homogeneous low add 64 adlls to the byte */
if (((patterns_byte_status[if_id][subphy_num]) &
(BYTE_HOMOGENEOUS_LOW | BYTE_SPLIT_OUT_MIX)) ==
(BYTE_HOMOGENEOUS_LOW | BYTE_SPLIT_OUT_MIX)) {
for (bit_num = 0; bit_num < BUS_WIDTH_IN_BITS; bit_num++) {
if (start_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] <= 31 &&
end_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] <= 31) {
start_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] +=
64;
end_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] += 64;
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_INFO,
("%s %s pattern %d if %d subphy %d bit %d added 64 "
"adll\n",
__func__, str_dir[mode], pattern_id, if_id,
subphy_num, bit_num));
}
}
}
/* calculations for the current pattern per subphy */
for (bit_num = 0; bit_num < BUS_WIDTH_IN_BITS; bit_num++) {
curr_win[bit_num] = end_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] -
start_win_db[pattern_loop_idx][if_id][subphy_num][bit_num] + 1;
curr_start_win[bit_num] =
start_win_db[pattern_loop_idx][if_id][subphy_num][bit_num];
curr_end_win[bit_num] =
end_win_db[pattern_loop_idx][if_id][subphy_num][bit_num];
}
opt_win = GET_MIN(opt_win, ddr3_tip_get_buf_min(curr_win));
vw_size[if_id][subphy_num] =
GET_MIN(vw_size[if_id][subphy_num], ddr3_tip_get_buf_min(curr_win));
/* final subphy window length */
final_subphy_win[if_id][subphy_num] = ddr3_tip_get_buf_min(curr_end_win) -
ddr3_tip_get_buf_max(curr_start_win) + 1;
waste_win = opt_win - final_subphy_win[if_id][subphy_num];
start_win_skew = ddr3_tip_get_buf_max(curr_start_win) -
ddr3_tip_get_buf_min(curr_start_win);
end_win_skew = ddr3_tip_get_buf_max(curr_end_win) -
ddr3_tip_get_buf_min(curr_end_win);
/* min/max updated with pattern change */
curr_end_win_min = ddr3_tip_get_buf_min(curr_end_win);
curr_start_win_max = ddr3_tip_get_buf_max(curr_start_win);
subphy_end_win[mode][if_id][subphy_num] =
GET_MIN(subphy_end_win[mode][if_id][subphy_num], curr_end_win_min);
subphy_start_win[mode][if_id][subphy_num] =
GET_MAX(subphy_start_win[mode][if_id][subphy_num], curr_start_win_max);
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_TRACE,
("%s, %s pat %d if %d subphy %d opt_win %d ",
__func__, str_dir[mode], pattern_id, if_id, subphy_num, opt_win));
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_TRACE,
("final_subphy_win %d waste_win %d "
"start_win_skew %d end_win_skew %d ",
final_subphy_win[if_id][subphy_num],
waste_win, start_win_skew, end_win_skew));
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("curr_start_win_max %d curr_end_win_min %d "
"subphy_start_win %d subphy_end_win %d\n",
curr_start_win_max, curr_end_win_min,
subphy_start_win[mode][if_id][subphy_num],
subphy_end_win[mode][if_id][subphy_num]));
/* valid window */
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("valid window, pat %d if %d subphy %d\n",
pattern_id, if_id, subphy_num));
for (bit_num = 0; bit_num < BUS_WIDTH_IN_BITS; bit_num++) {
final_start_win[if_id][subphy_num][bit_num] =
GET_MAX(final_start_win[if_id][subphy_num][bit_num],
curr_start_win[bit_num]);
final_end_win[if_id][subphy_num][bit_num] =
GET_MIN(final_end_win[if_id][subphy_num][bit_num],
curr_end_win[bit_num]);
} /* bit */
} /* subphy */
} /* if_id */
} /* pattern */
/* calculate valid window for each subphy */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (subphy_num = 0; subphy_num < subphy_max; subphy_num++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num);
if (patterns_byte_status[if_id][subphy_num] != BYTE_NOT_DEFINED) {
/*
* in case of bytes status which were found as mixed and low
* change the their status to be mixed only, due to the fact
* that we have already dealt with this bytes by adding 64 adlls
* to the low bytes
*/
if (patterns_byte_status[if_id][subphy_num] &
(BYTE_HOMOGENEOUS_LOW | BYTE_SPLIT_OUT_MIX))
patterns_byte_status[if_id][subphy_num] = BYTE_SPLIT_OUT_MIX;
if (rx_vw_pos[if_id][subphy_num] == 0) /* rx_vw_pos is initialized during tap tune */
pbs_max = 31 - 0xa;
else
pbs_max = 31;
/* continue if locked */
/*if (centralization_state[if_id][subphy_num] == 0) {*/
status = mv_ddr4_copt_get(mode, lambda[if_id][subphy_num],
final_start_win[if_id][subphy_num],
final_end_win[if_id][subphy_num],
pbs_result[if_id][subphy_num],
&copt[if_id][subphy_num]);
/*
* after copt the adll is moved to smaller value due to pbs compensation
* so the byte status might change, here we change the byte status to be
* homogeneous low in case the center of the ui after copt is moved below
* 31 adlls
*/
if(copt[if_id][subphy_num] <= 31)
patterns_byte_status[if_id][subphy_num] = BYTE_HOMOGENEOUS_LOW;
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_INFO,
("%s %s if %d subphy %d copt %d\n",
__func__, str_dir[mode], if_id, subphy_num, copt[if_id][subphy_num]));
if (status != MV_OK) {
/*
* TODO: print out error message(s) only when all points fail
* as temporary solution, replaced ERROR to TRACE debug level
*/
DEBUG_DDR4_CENTRALIZATION
(DEBUG_LEVEL_TRACE,
("%s %s copt calculation failed, "
"no valid window for subphy %d\n",
__func__, str_dir[mode], subphy_num));
/* set the byte to 0 (fail) and clean the status (continue with algorithm) */
vw_size[if_id][subphy_num] = 0;
status = MV_OK;
if (debug_mode == 0) {
/*
* TODO: print out error message(s) only when all points fail
* as temporary solution, commented out debug level set to TRACE
*/
/*
* ddr3_hws_set_log_level(DEBUG_BLOCK_CALIBRATION, DEBUG_LEVEL_TRACE);
*/
/* open relevant log and run function again for debug */
mv_ddr4_copt_get(mode, lambda[if_id][subphy_num],
final_start_win[if_id][subphy_num],
final_end_win[if_id][subphy_num],
pbs_result[if_id][subphy_num],
&copt[if_id][subphy_num]);
/*
* ddr3_hws_set_log_level(DEBUG_BLOCK_CALIBRATION, DEBUG_LEVEL_ERROR);
*/
} /* debug mode */
} /* status */
} /* byte not defined */
} /* subphy */
} /* if_id */
/* restore cs enable value*/
for (if_id = 0; if_id < MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG,
cs_ena_reg_val[if_id], MASK_ALL_BITS);
if (status != MV_OK)
return status;
}
return status;
}
/*
* mv_ddr4_copt_get function
* inputs:
* dir - direction; 0 is for rx, 1 for tx
* lambda - a pointer to adll to pbs ration multiplied by PBS_VAL_FACTOR
* vw_l - a pointer to valid window low limit in adll taps
* vw_h - a pointer to valid window high limit in adll taps
* outputs:
* pbs_result - a pointer to pbs new delay value; the function's output
* copt - optimal center of subphy in adll taps
* The function assumes initial pbs tap value is zero. Otherwise, it requires logic
* getting pbs value per dq and setting pbs_taps_per_dq array.
* It provides with a solution for a single subphy (8 bits).
* The calling function is responsible for any additional pbs taps for dqs
*/
static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_result, u8 *copt)
{
u8 center_per_dq[8];
u8 center_zone_low[8] = {0};
u8 center_zone_high[8] = {0};
u8 ext_center_zone_low[8] = {0};
u8 ext_center_zone_high[8] = {0};
u8 pbs_taps_per_dq[8] = {0};
u8 vw_per_dq[8];
u8 vw_zone_low[8] = {0};
u8 vw_zone_high[8] = {0};
u8 margin_vw[8] = {0};
u8 copt_val;
u8 dq_idx;
u8 center_zone_max_low = 0;
u8 center_zone_min_high = 128;
u8 vw_zone_max_low = 0;
u8 vw_zone_min_high = 128;
u8 min_vw = 63; /* minimum valid window between all bits */
u8 center_low_el;
u8 center_high_el;
/* lambda calculated as D * PBS_VALUE_FACTOR / d */
//printf("Copt::Debug::\t");
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
center_per_dq[dq_idx] = (vw_h[dq_idx] + vw_l[dq_idx]) / 2;
vw_per_dq[dq_idx] = 1 + (vw_h[dq_idx] - vw_l[dq_idx]);
if (min_vw > vw_per_dq[dq_idx])
min_vw = vw_per_dq[dq_idx];
}
/* calculate center zone */
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
center_low_el = center_low_element_get(dir, pbs_taps_per_dq[dq_idx], lambda[dq_idx], pbs_max);
if (center_per_dq[dq_idx] > center_low_el)
center_zone_low[dq_idx] = center_per_dq[dq_idx] - center_low_el;
center_high_el = center_high_element_get(dir, pbs_taps_per_dq[dq_idx], lambda[dq_idx], pbs_max);
center_zone_high[dq_idx] = center_per_dq[dq_idx] + center_high_el;
if (center_zone_max_low < center_zone_low[dq_idx])
center_zone_max_low = center_zone_low[dq_idx];
if (center_zone_min_high > center_zone_high[dq_idx])
center_zone_min_high = center_zone_high[dq_idx];
DEBUG_CALIBRATION(DEBUG_LEVEL_TRACE,
("center: low %d, high %d, max_low %d, min_high %d\n",
center_zone_low[dq_idx], center_zone_high[dq_idx],
center_zone_max_low, center_zone_min_high));
}
if (center_zone_min_high >= center_zone_max_low) { /* center zone visib */
/* set copt_val to high zone for rx */
copt_val = (dir == RX_DIR) ? center_zone_max_low : center_zone_min_high;
*copt = copt_val;
/* calculate additional pbs taps */
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
if (dir == RX_DIR)
pbs_result[dq_idx] = (copt_val - center_per_dq[dq_idx]) *
PBS_VAL_FACTOR / lambda[dq_idx];
else
pbs_result[dq_idx] = (center_per_dq[dq_idx] - copt_val) *
PBS_VAL_FACTOR / lambda[dq_idx];
}
return MV_OK;
} else { /* not center zone visib */
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
if ((center_zone_low[dq_idx] + 1) > (vw_per_dq[dq_idx] / 2 + vw_per_dq[dq_idx] % 2)) {
vw_zone_low[dq_idx] = (center_zone_low[dq_idx] + 1) -
(vw_per_dq[dq_idx] / 2 + vw_per_dq[dq_idx] % 2);
} else {
vw_zone_low[dq_idx] = 0;
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO,
("dq_idx %d, center zone low %d, vw_l %d, vw_l %d\n",
dq_idx, center_zone_low[dq_idx], vw_l[dq_idx], vw_h[dq_idx]));
DEBUG_CALIBRATION(DEBUG_LEVEL_INFO,
("vw_l[%d], vw_lh[%d], lambda[%d]\n",
vw_l[dq_idx], vw_h[dq_idx], lambda[dq_idx]));
}
vw_zone_high[dq_idx] = center_zone_high[dq_idx] + vw_per_dq[dq_idx] / 2;
if (vw_zone_max_low < vw_zone_low[dq_idx])
vw_zone_max_low = vw_zone_low[dq_idx];
if (vw_zone_min_high > vw_zone_high[dq_idx])
vw_zone_min_high = vw_zone_high[dq_idx];
DEBUG_CALIBRATION(DEBUG_LEVEL_TRACE,
("valid_window: low %d, high %d, max_low %d, min_high %d\n",
vw_zone_low[dq_idx], vw_zone_high[dq_idx],
vw_zone_max_low, vw_zone_min_high));
}
/* try to extend center zone */
if (vw_zone_min_high >= vw_zone_max_low) { /* vw zone visib */
center_zone_max_low = 0;
center_zone_min_high = 128;
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
margin_vw[dq_idx] = vw_per_dq[dq_idx] - min_vw;
if (center_zone_low[dq_idx] > margin_vw[dq_idx])
ext_center_zone_low[dq_idx] = center_zone_low[dq_idx] - margin_vw[dq_idx];
else
ext_center_zone_low[dq_idx] = 0;
ext_center_zone_high[dq_idx] = center_zone_high[dq_idx] + margin_vw[dq_idx];
if (center_zone_max_low < ext_center_zone_low[dq_idx])
center_zone_max_low = ext_center_zone_low[dq_idx];
if (center_zone_min_high > ext_center_zone_high[dq_idx])
center_zone_min_high = ext_center_zone_high[dq_idx];
DEBUG_CALIBRATION(DEBUG_LEVEL_TRACE,
("ext_center: low %d, high %d, max_low %d, min_high %d\n",
ext_center_zone_low[dq_idx], ext_center_zone_high[dq_idx],
center_zone_max_low, center_zone_min_high));
}
if (center_zone_min_high >= center_zone_max_low) { /* center zone visib */
/* get optimal center position */
copt_val = (dir == RX_DIR) ? center_zone_max_low : center_zone_min_high;
*copt = copt_val;
/* calculate additional pbs taps */
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
if (dir == 0) {
if (copt_val > center_per_dq[dq_idx])
pbs_result[dq_idx] = (copt_val - center_per_dq[dq_idx]) *
PBS_VAL_FACTOR / lambda[dq_idx];
else
pbs_result[dq_idx] = 0;
} else {
if (center_per_dq[dq_idx] > copt_val)
pbs_result[dq_idx] = (center_per_dq[dq_idx] - copt_val) *
PBS_VAL_FACTOR / lambda[dq_idx];
else
pbs_result[dq_idx] = 0;
}
if (pbs_result[dq_idx] > pbs_max)
pbs_result[dq_idx] = pbs_max;
}
return MV_OK;
} else { /* not center zone visib */
/*
* TODO: print out error message(s) only when all points fail
* as temporary solution, replaced ERROR to TRACE debug level
*/
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("lambda: %d, %d, %d, %d, %d, %d, %d, %d\n",
lambda[0], lambda[1], lambda[2], lambda[3],
lambda[4], lambda[5], lambda[6], lambda[7]));
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("vw_h: %d, %d, %d, %d, %d, %d, %d, %d\n",
vw_h[0], vw_h[1], vw_h[2], vw_h[3],
vw_h[4], vw_h[5], vw_h[6], vw_h[7]));
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("vw_l: %d, %d, %d, %d, %d, %d, %d, %d\n",
vw_l[0], vw_l[1], vw_l[2], vw_l[3],
vw_l[4], vw_l[5], vw_l[6], vw_l[7]));
for (dq_idx = 0; dq_idx < 8; dq_idx++) {
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("center: low %d, high %d, "
"max_low %d, min_high %d\n",
center_zone_low[dq_idx], center_zone_high[dq_idx],
center_zone_max_low, center_zone_min_high));
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("valid_window: low %d, high %d, "
"max_low %d, min_high %d\n",
vw_zone_low[dq_idx], vw_zone_high[dq_idx],
vw_zone_max_low, vw_zone_min_high));
DEBUG_DDR4_CENTRALIZATION(DEBUG_LEVEL_TRACE,
("ext_center: low %d, high %d, "
"max_low %d, min_high %d\n",
ext_center_zone_low[dq_idx],
ext_center_zone_high[dq_idx],
center_zone_max_low, center_zone_min_high));
}
return MV_FAIL;
}
} else { /* not vw zone visib; failed to find a single sample point */
return MV_FAIL;
}
}
return MV_OK;
}
/*
* mv_ddr4_dqs_reposition function gets copt to align to and returns pbs value per bit
* parameters:
* dir - direction; 0 is for rx, 1 for tx
* lambda - a pointer to adll to pbs ration multiplied by PBS_VAL_FACTOR
* pbs_result - a pointer to pbs new delay value; the function's output
* delta - signed; possilbe values: +0xa, 0x0, -0xa; for rx can be only negative
* copt - optimal center of subphy in adll taps
* dqs_pbs - optimal pbs
* The function assumes initial pbs tap value is zero. Otherwise, it requires logic
* getting pbs value per dq and setting pbs_taps_per_dq array.
* It provides with a solution for a single subphy (8 bits).
* The calling function is responsible for any additional pbs taps for dqs
*/
static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs)
{
u8 dq_idx;
u32 pbs_max_val = 0;
u32 lambda_avg = 0;
/* lambda calculated as D * X / d */