RISCVBase.core_desc

import "RISCVEncoding.core_desc"

InstructionSet RISCVBase extends RISCVEncoding {
    architectural_state {
        unsigned int XLEN;
        unsigned int INSTR_ALIGNMENT = 4;
        unsigned int RFS = 32;

        unsigned int fence = 0;
        unsigned int fencei = 1;
        unsigned int fencevmal = 2;
        unsigned int fencevmau = 3;

        // core registers
        register unsigned<XLEN> X[RFS] [[is_main_reg]];
        register unsigned<XLEN> PC [[is_pc]];

        // register aliases
        unsigned<XLEN>& ZERO = X[0];
        unsigned<XLEN>& RA = X[1];
        unsigned<XLEN>& SP = X[2];
        unsigned<XLEN>& GP = X[3];
        unsigned<XLEN>& TP = X[4];
        unsigned<XLEN>& T0 = X[5];
        unsigned<XLEN>& T1 = X[6];
        unsigned<XLEN>& T2 = X[7];
        unsigned<XLEN>& S0 = X[8];
        unsigned<XLEN>& S1 = X[9];
        unsigned<XLEN>& A0 = X[10];
        unsigned<XLEN>& A1 = X[11];
        unsigned<XLEN>& A2 = X[12];
        unsigned<XLEN>& A3 = X[13];
        unsigned<XLEN>& A4 = X[14];
        unsigned<XLEN>& A5 = X[15];
        unsigned<XLEN>& A6 = X[16];
        unsigned<XLEN>& A7 = X[17];
        unsigned<XLEN>& S2 = X[18];
        unsigned<XLEN>& S3 = X[19];
        unsigned<XLEN>& S4 = X[20];
        unsigned<XLEN>& S5 = X[21];
        unsigned<XLEN>& S6 = X[22];
        unsigned<XLEN>& S7 = X[23];
        unsigned<XLEN>& S8 = X[24];
        unsigned<XLEN>& S9 = X[25];
        unsigned<XLEN>& S10 = X[26];
        unsigned<XLEN>& S11 = X[27];
        unsigned<XLEN>& T3 = X[28];
        unsigned<XLEN>& T4 = X[29];
        unsigned<XLEN>& T5 = X[30];
        unsigned<XLEN>& T6 = X[31];

        // address spaces
        extern unsigned<8> MEM[1 << XLEN] [[is_main_mem]];
        extern unsigned<XLEN> FENCE[8];
        extern unsigned<8> RES[8]; // reservation address space

        // supplemental state register
        register unsigned<3> PRIV = 3;
        register unsigned<XLEN> DPC = 0;
    }

    functions {
        extern void raise(int irq, int mcause);
        extern void leave(int priv_lvl);
        extern void wait(int flag);
    }
}

InstructionSet RVPrivBase extends RISCVBase {
	    architectural_state {
        unsigned int CSR_SIZE = 4096;
        extern unsigned<XLEN> CSR[CSR_SIZE];
    }
}

InstructionSet RVFPBase extends RVPrivBase {
	    architectural_state {
        unsigned<32> FLEN = 32;
        unsigned<32> FFLAG_MASK = 0x1f;

        register unsigned<FLEN> F[32];
        unsigned<XLEN>& FCSR = CSR[3];
    }
}