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decoderMaskedMultiheadAttentionTemplate.h
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decoderMaskedMultiheadAttentionTemplate.h
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/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include "tensorrt_llm/common/cudaTypeUtils.cuh"
#include "tensorrt_llm/common/memoryUtils.h"
#include "tensorrt_llm/kernels/decoderMaskedMultiheadAttention.h"
#include "tensorrt_llm/kernels/decoderMaskedMultiheadAttentionUtils.h"
#include "tensorrt_llm/kernels/gptKernels.h"
#include "tensorrt_llm/kernels/kvCacheUtils.h"
#include <assert.h>
#include <float.h>
#include <type_traits>
// Multi-block mmha kernel can only be selected when CUDA >= 11.7
#if (CUDART_VERSION >= 11070)
#define ENABLE_MULTI_BLOCK_OPTION
#endif
#ifdef ENABLE_MULTI_BLOCK_OPTION
#include <cub/block/block_reduce.cuh>
#include <cuda/atomic>
#include <cuda/std/bit>
#endif // ENABLE_MULTI_BLOCK_OPTION
namespace tensorrt_llm
{
namespace kernels
{
// #define MMHA_USE_HMMA_FOR_REDUCTION
// Below are knobs to extend FP32 accumulation for higher FP16 accuracy
// Does not seem to affect the accuracy that much
#define MMHA_USE_FP32_ACUM_FOR_FMA
// Seems to slightly improve the accuracy
#define MMHA_USE_FP32_ACUM_FOR_OUT
#if 0 && defined(MMHA_USE_FP32_ACUM_FOR_OUT)
// Does not seem to improve the accuracy
//#define MMHA_USE_FP32_ACUM_FOR_LOGITS
#endif
namespace mmha
{
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// We use the following terminology to describe the different dimensions.
//
// B: Batch size (number of sequences),
// L: Sequence length,
// D: Hidden dimension,
// H: Number of heads,
// Dh: Hidden dimension per head - Dh = D / H.
//
// The different kernels assign a threadblock for B x H pair. The grid has size (1, B, H). We use
// 256 threads per block to maximum occupancy and performance.
//
// Each threadblock loads Dh values from Q and its associated bias. The kernels run a loop to
// compute Q * K^T where K is loaded from a cache buffer -- except for the current timestep. The
// cache buffer helps with memory accesses and contains keys with bias.
//
// The layout of the cache buffer for the keys/values is [B, H, L, Dh]
// where the fastest moving dimension (contiguous data) is the rightmost one.
// Contiguous threads will read one hidden_dimension per LDG unless we need more than 32 threads.
//
// The different kernels use 1 ~ 32 threads per key (THREADS_PER_KEY). The size of the LDGs
// is always 16bytes (8 bytes for 8bit cache). Each thread sums Dh / THREADS_PER_KEY elements. At
// the end of each iteration of the Q * K^T loop, we perform a reduction between lanes using an
// HMMA instruction (Tensor Core). Each Q * K^T value is stored in shared memory in FP32.
//
// After that loop, a parallel softmax is computed across the different Q * K^T values stored in
// shared memory.
//
// The kernel ends with a loop over the values in V. We use THREADS_PER_VALUE to control how many
// timesteps are computed by loop iteration. As with the keys, the values are read from a cache
// except for the current timestep. The layout of the cache buffer for the values is same as the key,
// which is [B, H, L, Dh].
//
// Note that we have remapped key layout to make sure it shares the same pattern as value [B, H, L, Dh].
// It helps coalescing memory access, and reducing register pressure.
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int Dh_MAX>
struct Qk_vec_m_
{
};
template <>
struct Qk_vec_m_<float, 32>
{
using Type = float;
};
template <>
struct Qk_vec_m_<float, 64>
{
using Type = float2;
};
template <>
struct Qk_vec_m_<float, 128>
{
using Type = float4;
};
template <>
struct Qk_vec_m_<float, 256>
{
using Type = float4;
};
template <>
struct Qk_vec_m_<uint16_t, 32>
{
using Type = uint32_t;
};
template <>
struct Qk_vec_m_<uint16_t, 64>
{
using Type = uint32_t;
};
template <>
struct Qk_vec_m_<uint16_t, 128>
{
using Type = uint2;
};
template <>
struct Qk_vec_m_<uint16_t, 256>
{
using Type = uint4;
};
#ifdef ENABLE_BF16
template <>
struct Qk_vec_m_<__nv_bfloat16, 32>
{
using Type = __nv_bfloat162;
};
template <>
struct Qk_vec_m_<__nv_bfloat16, 64>
{
using Type = __nv_bfloat162;
};
template <>
struct Qk_vec_m_<__nv_bfloat16, 128>
{
using Type = bf16_4_t;
};
template <>
struct Qk_vec_m_<__nv_bfloat16, 256>
{
using Type = bf16_8_t;
};
#endif // ENABLE_BF16
#ifdef ENABLE_FP8
template <>
struct Qk_vec_m_<__nv_fp8_e4m3, 32>
{
using Type = fp8_4_t;
};
template <>
struct Qk_vec_m_<__nv_fp8_e4m3, 64>
{
using Type = fp8_4_t;
};
template <>
struct Qk_vec_m_<__nv_fp8_e4m3, 128>
{
using Type = fp8_4_t;
};
template <>
struct Qk_vec_m_<__nv_fp8_e4m3, 256>
{
using Type = fp8_4_t;
};
#endif // ENABLE_FP8
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int Dh>
struct Qk_vec_k_
{
using Type = typename Qk_vec_m_<T, Dh>::Type;
};
#ifdef ENABLE_FP8
template <>
struct Qk_vec_k_<__nv_fp8_e4m3, 32>
{
using Type = float4;
};
template <>
struct Qk_vec_k_<__nv_fp8_e4m3, 64>
{
using Type = float4;
};
template <>
struct Qk_vec_k_<__nv_fp8_e4m3, 128>
{
using Type = float4;
};
template <>
struct Qk_vec_k_<__nv_fp8_e4m3, 256>
{
using Type = float4;
};
#endif // ENABLE_FP8
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int V_VEC_SIZE>
struct V_vec_m_
{
};
template <>
struct V_vec_m_<float, 1>
{
using Type = float;
};
template <>
struct V_vec_m_<float, 2>
{
using Type = float2;
};
template <>
struct V_vec_m_<float, 4>
{
using Type = float4;
};
template <>
struct V_vec_m_<float, 8>
{
using Type = Float8_;
};
template <>
struct V_vec_m_<uint16_t, 2>
{
using Type = uint32_t;
};
template <>
struct V_vec_m_<uint16_t, 4>
{
using Type = uint2;
};
template <>
struct V_vec_m_<uint16_t, 8>
{
using Type = uint4;
};
#ifdef ENABLE_BF16
template <>
struct V_vec_m_<__nv_bfloat16, 2>
{
using Type = __nv_bfloat162;
};
template <>
struct V_vec_m_<__nv_bfloat16, 4>
{
using Type = bf16_4_t;
};
template <>
struct V_vec_m_<__nv_bfloat16, 8>
{
using Type = bf16_8_t;
};
#endif // ENABLE_BF16
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int V_VEC_SIZE>
struct V_vec_k_
{
using Type = typename V_vec_m_<T, V_VEC_SIZE>::Type;
};
#ifdef ENABLE_FP8
template <>
struct V_vec_k_<__nv_fp8_e4m3, 4>
{
using Type = float4;
};
template <>
struct V_vec_k_<__nv_fp8_e4m3, 8>
{
using Type = float4;
};
template <>
struct V_vec_k_<__nv_fp8_e4m3, 16>
{
using Type = float4;
};
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
// Reuse V_vec traits as key and value share the same layout.
template <typename T, int K_VEC_SIZE>
struct K_vec_m_
{
using Type = typename V_vec_m_<T, K_VEC_SIZE>::Type;
};
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int K_VEC_SIZE>
struct K_vec_k_
{
using Type = typename K_vec_m_<T, K_VEC_SIZE>::Type;
};
////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef MMHA_USE_FP32_ACUM_FOR_FMA
template <typename T>
struct Qk_vec_acum_fp32_
{
};
template <>
struct Qk_vec_acum_fp32_<float>
{
using Type = float;
};
template <>
struct Qk_vec_acum_fp32_<float2>
{
using Type = float2;
};
template <>
struct Qk_vec_acum_fp32_<float4>
{
using Type = float4;
};
// template<> struct Qk_vec_acum_fp32_<uint16_t> { using Type = float; };
template <>
struct Qk_vec_acum_fp32_<uint32_t>
{
using Type = float2;
};
template <>
struct Qk_vec_acum_fp32_<uint2>
{
using Type = Float4_;
};
template <>
struct Qk_vec_acum_fp32_<uint4>
{
using Type = Float8_;
};
template <>
struct Qk_vec_acum_fp32_<__nv_bfloat16>
{
using Type = float;
};
template <>
struct Qk_vec_acum_fp32_<__nv_bfloat162>
{
using Type = float2;
};
template <>
struct Qk_vec_acum_fp32_<bf16_4_t>
{
using Type = Float4_;
};
template <>
struct Qk_vec_acum_fp32_<bf16_8_t>
{
using Type = Float8_;
};
#ifdef ENABLE_FP8
// template<>
// struct Qk_vec_acum_fp32_<fp8_2_t> {
// using Type = float2;
// };
template <>
struct Qk_vec_acum_fp32_<fp8_4_t>
{
using Type = Float4_;
};
// template<>
// struct Qk_vec_acum_fp32_<fp8_8_t> {
// using Type = Float4_;
// };
#endif // ENABLE_FP8
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T>
struct K_vec_acum_fp32_
{
};
template <>
struct K_vec_acum_fp32_<float>
{
using Type = float;
};
template <>
struct K_vec_acum_fp32_<float2>
{
using Type = float2;
};
template <>
struct K_vec_acum_fp32_<float4>
{
using Type = float4;
};
template <>
struct K_vec_acum_fp32_<Float8_>
{
using Type = Float8_;
};
template <>
struct K_vec_acum_fp32_<uint32_t>
{
using Type = float2;
};
template <>
struct K_vec_acum_fp32_<uint2>
{
using Type = Float4_;
};
template <>
struct K_vec_acum_fp32_<uint4>
{
using Type = Float8_;
};
template <>
struct K_vec_acum_fp32_<__nv_bfloat16>
{
using Type = float;
};
template <>
struct K_vec_acum_fp32_<__nv_bfloat162>
{
using Type = float2;
};
template <>
struct K_vec_acum_fp32_<bf16_4_t>
{
using Type = Float4_;
};
template <>
struct K_vec_acum_fp32_<bf16_8_t>
{
using Type = Float8_;
};
#ifdef ENABLE_FP8
// template<>
// struct K_vec_acum_fp32_<fp8_2_t> {
// using Type = float2;
// };
template <>
struct K_vec_acum_fp32_<fp8_4_t>
{
using Type = Float4_;
};
// template<>
// struct K_vec_acum_fp32_<fp8_8_t> {
// using Type = Float4_;
// };
#endif // ENABLE_FP8
#endif // MMHA_USE_FP32_ACUM_FOR_FMA
////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef MMHA_USE_FP32_ACUM_FOR_OUT
template <typename T>
struct V_vec_acum_fp32_
{
};
template <>
struct V_vec_acum_fp32_<float>
{
using Type = float;
};
template <>
struct V_vec_acum_fp32_<float2>
{
using Type = float2;
};
template <>
struct V_vec_acum_fp32_<float4>
{
using Type = float4;
};
template <>
struct V_vec_acum_fp32_<uint32_t>
{
using Type = float2;
};
template <>
struct V_vec_acum_fp32_<uint2>
{
using Type = Float4_;
};
template <>
struct V_vec_acum_fp32_<uint4>
{
using Type = Float8_;
};
#ifdef ENABLE_BF16
template <>
struct V_vec_acum_fp32_<__nv_bfloat162>
{
using Type = float2;
};
template <>
struct V_vec_acum_fp32_<bf16_4_t>
{
using Type = Float4_;
};
template <>
struct V_vec_acum_fp32_<bf16_8_t>
{
using Type = Float8_;
};
#endif // ENABLE_BF16
#ifdef ENABLE_FP8
// template<>
// struct V_vec_acum_fp32_<fp8_2_t> {
// using Type = float2;
// };
template <>
struct V_vec_acum_fp32_<fp8_4_t>
{
using Type = Float4_;
};
// template<>
// struct V_vec_acum_fp32_<fp8_8_t> {
// using Type = Float4_;
// };
#endif // ENABLE_FP8
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename Tout, typename Tin>
__inline__ __device__ constexpr Tout vec_conversion(const Tin& x)
{
static_assert(std::is_same<Tout, Tin>::value, "Type mismatch");
return x;
}
#ifdef ENABLE_FP8
// fp8_t
template <>
__inline__ __device__ float vec_conversion<float, __nv_fp8_e4m3>(const __nv_fp8_e4m3& a)
{
return float(a);
}
template <>
__inline__ __device__ __nv_fp8_e4m3 vec_conversion<__nv_fp8_e4m3, float>(const float& a)
{
return __nv_fp8_e4m3(a);
}
// fp8_2_t
template <>
__inline__ __device__ float2 vec_conversion<float2, fp8_2_t>(const fp8_2_t& a)
{
return float2(a);
}
template <>
__inline__ __device__ fp8_2_t vec_conversion<fp8_2_t, float2>(const float2& a)
{
return fp8_2_t(a);
}
// fp8_4_t
template <>
__inline__ __device__ float4 vec_conversion<float4, fp8_4_t>(const fp8_4_t& a)
{
return float4(a);
}
template <>
__inline__ __device__ fp8_4_t vec_conversion<fp8_4_t, float4>(const float4& a)
{
return fp8_4_t(a);
}
#endif // ENABLE_FP8
////////////////////////////////////////////////////////////////////////////////////////////////////
template <int THREADS_PER_KEY, typename K_vec, int N>
inline __device__ float qk_dot_(const K_vec (&q)[N], const K_vec (&k)[N])
{
#ifdef MMHA_USE_FP32_ACUM_FOR_FMA
using K_vec_acum = typename K_vec_acum_fp32_<K_vec>::Type;
#else
using K_vec_acum = K_vec;
#endif
// Compute the parallel products for Q*K^T (treat vector lanes separately).
K_vec_acum qk_vec = mul<K_vec_acum, K_vec, K_vec>(q[0], k[0]);
#pragma unroll
for (int ii = 1; ii < N; ++ii)
{
qk_vec = fma(q[ii], k[ii], qk_vec);
}
// Finalize the reduction across lanes.
float qk = sum(qk_vec);
#pragma unroll
for (int mask = THREADS_PER_KEY / 2; mask >= 1; mask /= 2)
{
qk += __shfl_xor_sync(uint32_t(-1), qk, mask);
}
return qk;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, int THREADS_PER_KEY>
struct Qk_dot
{
template <typename K_vec, int N>
static inline __device__ float dot(const K_vec (&q)[N], const K_vec (&k)[N])
{
return qk_dot_<THREADS_PER_KEY>(q, k);
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float4 hmma_fp32(const uint2& a, uint32_t b)
{
float4 c;
float zero = 0.f;
asm volatile(
"mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 \n"
" {%0, %1, %2, %3}, \n"
" {%4, %5}, \n"
" {%6}, \n"
" {%7, %7, %7, %7}; \n"
: "=f"(c.x), "=f"(c.y), "=f"(c.z), "=f"(c.w)
: "r"(a.x) "r"(a.y), "r"(b), "f"(zero));
return c;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <int N>
inline __device__ float qk_hmma_dot_(const uint32_t (&q)[N], const uint32_t (&k)[N])
{
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 750
#ifdef MMHA_USE_FP32_ACUM_FOR_FMA
using K_vec_acum = typename K_vec_acum_fp32_<uint32_t>::Type;
#else
using K_vec_acum = uint32_t;
#endif
K_vec_acum qk_vec = mul<K_vec_acum, uint32_t, uint32_t>(q[0], k[0]);
#pragma unroll
for (int ii = 1; ii < N; ++ii)
{
qk_vec = fma(q[ii], k[ii], qk_vec);
}
#ifdef MMHA_USE_FP32_ACUM_FOR_FMA
uint32_t qk_vec_ = float2_to_half2(qk_vec);
return hmma_fp32(make_uint2(qk_vec_, 0u), 0x3c003c00u).x;
#else
return hmma_fp32(make_uint2(qk_vec, 0u), 0x3c003c00u).x;
#endif
#else
return 0.f;
#endif
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <>
struct Qk_dot<uint16_t, 4>
{
template <typename K_vec, int N>
static inline __device__ float dot(const K_vec (&q)[N], const K_vec (&k)[N])
{
return qk_dot_<4>(q, k);
}
template <int N>
static inline __device__ float dot(const uint32_t (&q)[N], const uint32_t (&k)[N])
{
#if __CUDA_ARCH__ >= 750 && defined(MMHA_USE_HMMA_FOR_REDUCTION)
return qk_hmma_dot_(q, k);
#else
return qk_dot_<4>(q, k);
#endif // defined MMHA_USE_HMMA_FOR_REDUCTION
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
template <int WARPS_PER_BLOCK, int WARP_SIZE = 32>
inline __device__ float block_sum(float* red_smem, float sum)
{
// Decompose the thread index into warp / lane.
int warp = threadIdx.x / WARP_SIZE;
int lane = threadIdx.x % WARP_SIZE;
// Compute the sum per warp.
#pragma unroll
for (int mask = WARP_SIZE / 2; mask >= 1; mask /= 2)
{
sum += __shfl_xor_sync(uint32_t(-1), sum, mask);
}
// Warp leaders store the data to shared memory.
if (lane == 0)
{
red_smem[warp] = sum;
}
// Make sure the data is in shared memory.
__syncthreads();
// The warps compute the final sums.
if (lane < WARPS_PER_BLOCK)
{
sum = red_smem[lane];
}
// Parallel reduction inside the warp.
#pragma unroll
for (int mask = WARPS_PER_BLOCK / 2; mask >= 1; mask /= 2)
{
sum += __shfl_xor_sync(uint32_t(-1), sum, mask);
}
// Broadcast to other threads.
return __shfl_sync(uint32_t(-1), sum, 0);
}
#if defined(MMHA_USE_FP32_ACUM_FOR_LOGITS)
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float cast_to_float(float u)
{
return u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float2 cast_to_float(float2 u)
{
return u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float4 cast_to_float(float4 u)
{
return u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float4_ cast_to_float(Float4_ u)
{
return u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float8_ cast_to_float(Float8_ u)
{
return u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float2 cast_to_float(uint32_t u)
{
return half2_to_float2(u);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float4_ cast_to_float(uint2 u)
{
Float4_ tmp;
tmp.x = half2_to_float2(u.x);
tmp.y = half2_to_float2(u.y);
return tmp;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float8_ cast_to_float(uint4 u)
{
Float8_ tmp;
tmp.x = half2_to_float2(u.x);
tmp.y = half2_to_float2(u.y);
tmp.z = half2_to_float2(u.z);
tmp.w = half2_to_float2(u.w);
return tmp;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ float2 cast_to_float(__nv_bfloat162 u)
{
float2 tmp;
tmp = __bfloat1622float2(u);
return tmp;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float4_ cast_to_float(bf16_4_t u)
{
Float4_ tmp;
tmp.x = __bfloat1622float2(u.x);
tmp.y = __bfloat1622float2(u.y);
return tmp;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ Float8_ cast_to_float(bf16_8_t u)
{
Float8_ tmp;
tmp.x = __bfloat1622float2(u.x);
tmp.y = __bfloat1622float2(u.y);
tmp.z = __bfloat1622float2(u.z);
tmp.w = __bfloat1622float2(u.w);
return tmp;
}
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T>
inline __device__ __host__ T divUp(T m, T n)
{
return (m + n - 1) / n;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T>
inline __device__ __host__ T div(T m, T n)
{
return m / n;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T>
struct kernel_type_t
{
using Type = T;
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// Compute the largest supported head size (dh_max). It must be the smallest power-of-2 that is not strictly smaller
// than the head size (dh).
inline __device__ __host__ constexpr unsigned dh_max(unsigned dh)
{
return next_power_of_two(mmha::const_max(dh, 32u));
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T>
inline __device__ __host__ constexpr unsigned threads_per_value(unsigned dh_max)
{
return dh_max * sizeof(T) / 16;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, unsigned Dh_MAX>
inline __device__ __host__ constexpr unsigned threads_per_key()
{
// Since we want to perform the reduction entirely within a warp, the number of threads per key
// is capped at 32.
constexpr unsigned threads = (unsigned) (Dh_MAX * sizeof(T) / 16u);
if ((threads & (threads - 1)) != 0)
{
assert(false); // Not a power of two.
}
return std::min(32u, threads);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline __device__ constexpr uint32_t shfl_mask(int threads)
{
assert(threads <= 32);
return threads == 32 ? -1u : (1u << threads) - 1u;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <typename T, typename T_VEC, unsigned VECS_PER_CHUNK>
__device__ inline constexpr uint2 chunk_index(unsigned tidx)
{
// The chunk associated with the thread.
auto const idx_chunk = tidx / VECS_PER_CHUNK;
// The position of the T_VEC vector in that chunk associated with the thread.
static_assert(sizeof(T_VEC) % sizeof(T) == 0);
unsigned constexpr kVecSize{sizeof(T_VEC) / sizeof(T)};
auto const idx_vec = (tidx % VECS_PER_CHUNK) * kVecSize;
return uint2{idx_chunk, idx_vec};
}
////////////////////////////////////////////////////////////////////////////////////////////////////
template <
// The type of the inputs. Supported types: float, uint16_t, nv_bfloat16.
typename T,
// The type of the cache.
typename Tcache,
// Type of struct containing KV cache
typename KVCacheBuffer,
// The hidden dimension per head.
unsigned Dh,
// The number of threads in a threadblock.
unsigned THREADS_PER_BLOCK,
// Whether cross attention is enabled
bool DO_CROSS_ATTENTION,