Hardwired $zero

[mumbel]

hopefully didn't miss this in MIPS/

$r0 is the $zero register and according to the manual is hardwired 0x0. Being available to write results, but discarded, and to use as the immediate 0x0.

Is there anyway to enforce this in ghidra from a higher level in the processor definitions, or would it have to be at the instruction level. Guessing if the latter it would be a pre/post macro to ensure $zero is 0x0 upon entry and exit of the instruction where $zero is allowed

I have seen some instructions that are using dst $zero (setting flags probably?) and in the same function use $zero as imm 0x0, completely confusing the decompiler

Looks like AARCH64 does it with tables exporting either the reg or a tmp=0

Nvmd, MIPS has this logic as well

Is this what the WARNING: Removing unreachable block (ram,0xaddr) messages are?

[mumbel]

@piruzzolo looks like GitHub ate your comment, that's exactly what I was asking for

[teaalltr]

LUL wut!? It's disappeared, weird

I rewrite it

"That would be useful for RISC-V too"

[mumbel]

Looks like the approach used in MIPS and ARM64 doesn't allow for writing to zero register with side-effects. Getting Low-level Error: Assignment to constant at when destination register is zero in decompiler. No real good example of this yet, but addi zero,zero,0x0 occurs often, (though this is the nop once I add the psuedo)