Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Ethernet on OX810(D)SE (Western Digital MyBook World Edition II NAS) #2

Open
Ykidia opened this issue Aug 27, 2022 · 1 comment
Open

Ethernet on OX810(D)SE (Western Digital MyBook World Edition II NAS) #2

Ykidia opened this issue Aug 27, 2022 · 1 comment

Comments

@Ykidia
Copy link

Ykidia commented Aug 27, 2022 •
edited
Loading

Hello! Again I need your help.
Now I can not get ethernet working on my WD MBWE II with kernel 5.15.
I performed all, I think, your recommendations (some of them described here) about how to enable the networking adapter incorporated in OX810(D)SE, previously was as Synopsys GMAC and now it is STMMAC, Oxford variation.

This is my ox810se.dtsi:

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
 *
 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
 */

#include <dt-bindings/clock/oxsemi,ox810se.h>
#include <dt-bindings/reset/oxsemi,ox810se.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "oxsemi,ox810se";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			clocks = <&armclk>;
		};
	};

	memory {
		device_type = "memory";
		/* Max 256MB @ 0x48000000 */
		reg = <0x48000000 0x10000000>;
	};

	clocks {
		osc: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		gmacclk: gmacclk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		rpsclk: rpsclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&osc>;
		};

		pll400: pll400 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <733333333>;
		};

		sysclk: sysclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clocks = <&pll400>;
		};

		armclk: armclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clocks = <&pll400>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc>;

		usb: usb@40200000 {
			compatible = "oxsemi,ox810se-ehci";
			reg = <0x40200000 0x200000>;
			interrupts = <7>;
			clocks = <&stdclk 5>;
			clock-names = "usb";
			resets = <&reset 4>, <&reset 5>;
			reset-names = "host", "phy";
			status = "disabled";

			oxsemi,input-pol-invert;
			oxsemi,output-pol-invert;
			oxsemi,patch-detect;

			/* Regmap for sys registers */
			oxsemi,sys-ctrl = <&sys>;
		};

		etha: ethernet@40400000 {
			compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
			reg = <0x40400000 0x2000>;
			interrupts = <8>;
			interrupt-names = "macirq";
			mac-address = [000000000000]; /* Filled in by U-Boot */
			phy-mode = "rgmii";

			clocks = <&stdclk 6>, <&gmacclk>;
			clock-names = "gmac", "stmmaceth";
			resets = <&reset 6>;

			/* Regmap for sys registers */
			oxsemi,sys-ctrl = <&sys>;

			status = "disabled";
		};

		apb-bridge@44000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0 0x44000000 0x1000000>;

			pinctrl: pinctrl {
				compatible = "oxsemi,ox810se-pinctrl";

				/* Regmap for sys registers */
				oxsemi,sys-ctrl = <&sys>;

				pinctrl_uart0: uart0 {
					uart0a {
						pins = "gpio31";
						function = "fct3";
					};
					uart0b {
						pins = "gpio32";
						function = "fct3";
					};
				};

				pinctrl_uart0_modem: uart0_modem {
					uart0c {
						pins = "gpio27";
						function = "fct3";
					};
					uart0d {
						pins = "gpio28";
						function = "fct3";
					};
					uart0e {
						pins = "gpio29";
						function = "fct3";
					};
					uart0f {
						pins = "gpio30";
						function = "fct3";
					};
					uart0g {
						pins = "gpio33";
						function = "fct3";
					};
					uart0h {
						pins = "gpio34";
						function = "fct3";
					};
				};

				pinctrl_uart1: uart1 {
					uart1a {
						pins = "gpio20";
						function = "fct3";
					};
					uart1b {
						pins = "gpio22";
						function = "fct3";
					};
				};

				pinctrl_uart1_modem: uart1_modem {
					uart1c {
						pins = "gpio8";
						function = "fct3";
					};
					uart1d {
						pins = "gpio9";
						function = "fct3";
					};
					uart1e {
						pins = "gpio23";
						function = "fct3";
					};
					uart1f {
						pins = "gpio24";
						function = "fct3";
					};
					uart1g {
						pins = "gpio25";
						function = "fct3";
					};
					uart1h {
						pins = "gpio26";
						function = "fct3";
					};
				};

				pinctrl_uart2: uart2 {
					uart2a {
						pins = "gpio6";
						function = "fct3";
					};
					uart2b {
						pins = "gpio7";
						function = "fct3";
					};
				};

				pinctrl_uart2_modem: uart2_modem {
					uart2c {
						pins = "gpio0";
						function = "fct3";
					};
					uart2d {
						pins = "gpio1";
						function = "fct3";
					};
					uart2e {
						pins = "gpio2";
						function = "fct3";
					};
					uart2f {
						pins = "gpio3";
						function = "fct3";
					};
					uart2g {
						pins = "gpio4";
						function = "fct3";
					};
					uart2h {
						pins = "gpio5";
						function = "fct3";
					};
				};

				pinctrl_usb_clko: usb_clko {
					clko {
						pins = "gpio10";
						function = "fct2";
					};
				};

				pinctrl_usb_porta: usb_porta {
					porta {
						pins = "gpio23", "gpio24";
						function = "fct1";
					};
				};

				pinctrl_usb_portb: usb_portb {
					portb {
						pins = "gpio25", "gpio26";
						function = "fct1";
					};
				};

				pinctrl_usb_portc: usb_portc {
					portc {
						pins = "gpio27", "gpio28";
						function = "fct1";
					};
				};
			};

			gpio0: gpio@0 {
				compatible = "oxsemi,ox810se-gpio";
				reg = <0x000000 0x100000>;
				interrupts = <21>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				ngpios = <32>;
				oxsemi,gpio-bank = <0>;
				gpio-ranges = <&pinctrl 0 0 32>;
			};

			gpio1: gpio@100000 {
				compatible = "oxsemi,ox810se-gpio";
				reg = <0x100000 0x100000>;
				interrupts = <22>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				ngpios = <3>;
				oxsemi,gpio-bank = <1>;
				gpio-ranges = <&pinctrl 0 32 3>;
			};

			uart0: serial@200000 {
			       compatible = "ns16550a";
			       reg = <0x200000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <23>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART1>;
			};

			uart1: serial@300000 {
			       compatible = "ns16550a";
			       reg = <0x300000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <24>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART2>;
			};

			uart2: serial@900000 {
			       compatible = "ns16550a";
			       reg = <0x900000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <29>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART3>;
			};

			uart3: serial@a00000 {
			       compatible = "ns16550a";
			       reg = <0xa00000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <30>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART4>;
			};
		};

		apb-bridge@45000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0 0x45000000 0x1000000>;

			sys: sys-ctrl@0 {
				compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
				reg = <0x000000 0x100000>;

				reset: reset-controller {
					compatible = "oxsemi,ox810se-reset";
					#reset-cells = <1>;
				};

				stdclk: stdclk {
					compatible = "oxsemi,ox810se-stdclk";
					#clock-cells = <1>;
				};
			};

			rps@300000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "simple-bus";
				ranges = <0 0x300000 0x100000>;

				intc: interrupt-controller@0 {
					compatible = "oxsemi,ox810se-rps-irq";
					interrupt-controller;
					reg = <0 0x200>;
					#interrupt-cells = <1>;
					valid-mask = <0xffffffff>;
					clear-mask = <0xffffffff>;
				};

				timer0: timer@200 {
					compatible = "oxsemi,ox810se-rps-timer";
					reg = <0x200 0x40>;
					clocks = <&rpsclk>;
					interrupts = <4 5>;
				};
			};

			dma: dma@600000 {
				compatible = "oxsemi,ox810se-dma";
				reg = <0x600000 0x100000
				       0xc00000 0x100000>;
				reg-names = "dma", "sgdma";
				interrupts = <13 14 15 16 20>;
				clocks = <&stdclk 1>;
				resets = <&reset 8>, <&reset 24>;
				reset-names = "dma", "sgdma";

				/* Encodes the authorized memory types */
				oxsemi,targets-types = <
					0x45900000 0x45a00000 0  /* SATA */
					0x42000000 0x43000000 0  /* SATA DATA */
					0x48000000 0x58000000 15 /* DDR */
					0x58000000 0x58020000 15 /* SRAM */
					>;

				#dma-cells = <1>;
				dma-channels = <5>;
			};
		};

		sata: sata@45900000 {
			/* System SG DMA */
			dmas = <&dma 0>;
			dma-names = "sgdma";

			compatible = "plxtech,nas782x-sata";
			      /*   ports          */
			reg = <0x45900000 0x100000>,
			      /*   data           */
			      <0x42000000 0x1000000>;
			reg-names = "sata", "sata-data";
			interrupts = <18>;
			clocks = <&stdclk 3>;
			resets = <&reset 11>, <&reset 12>, <&reset 13>;
			reset-names = "sata", "link", "phy";
			nr-ports = <1>;
			status = "disabled";
		};
	};
};

and ox810se-wd-mbwe.dts:

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition
 *
 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
 */

/dts-v1/;
#include "ox810se.dtsi"

/ {
	model = "Western Digital My Book World Edition";

	compatible = "wd,mbwe", "oxsemi,ox810se";

	chosen {
		bootargs = "console=ttyS1,115200n8 earlyprintk=serial";
	};

	memory {
		/* 128Mbytes DDR */
		reg = <0x48000000 0x8000000>;
	};

	aliases {
		serial1 = &uart1;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		#address-cells = <1>;
		#size-cells = <0>;
		poll-interval = <100>;

		power {
			label = "power";
			gpios = <&gpio0 0 1>;
			linux,code = <0x198>;
		};

		recovery {
			label = "recovery";
			gpios = <&gpio0 4 1>;
			linux,code = <0xab>;
		};
	};

	leds {
		compatible = "gpio-leds";

		a0 {
			label = "activity0";
			gpios = <&gpio0 25 0>;
			default-state = "keep";
		};

		a1 {
			label = "activity1";
			gpios = <&gpio0 26 0>;
			default-state = "keep";
		};

		a2 {
			label = "activity2";
			gpios = <&gpio0 5 0>;
			default-state = "keep";
		};

		a3 {
			label = "activity3";
			gpios = <&gpio0 6 0>;
			default-state = "keep";
		};

		a4 {
			label = "activity4";
			gpios = <&gpio0 7 0>;
			default-state = "keep";
		};

		a5 {
			label = "activity5";
			gpios = <&gpio1 2 0>;
			default-state = "keep";
		};
	};

	i2c-gpio {
		compatible = "i2c-gpio";
		gpios = <&gpio0 3 0 /* sda */
			 &gpio0 2 0 /* scl */
			 >;
		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;

		rtc0: rtc@48 {
			compatible = "st,m41t00";
			reg = <0x68>;
		};
	};
};

&uart1 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&dma {
	status = "okay";
};

&sata {
	status = "okay";
	nr-ports = <2>;
};

&usb {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_clko &pinctrl_usb_porta>;

	/* USB HUB Reset Line */
	hub-gpio = <&gpio0 27 1>;
};

&etha {
	status = "okay";
};

Then I selected in kernel configurator:

Device Drivers > Network device support > PHY Device support and infrastructure
    <*>   LSI ET1011C PHY
Device Drivers > Network device support > Ethernet driver support
    [*]   STMicroelectronics devices
      <*>     STMicroelectronics Multi-Gigabit Ethernet driver
      [ ]       Support for STMMAC Selftests
         <*>       STMMAC Platform bus support
         < >         Support for snps,dwc-qos-ethernet.txt DT binding.
         < >         Generic driver for DWMAC
         <*>         Oxford Semiconductor OXNAS dwmac support

And also I had to turn on MDIO, because without this there was additional error in kernel log:

[    0.633201] oxnas-dwmac 40400000.ethernet: IRQ eth_wake_irq not found
[    0.639699] oxnas-dwmac 40400000.ethernet: IRQ eth_lpi not found
[    0.645979] oxnas-dwmac 40400000.ethernet: PTP uses main clock
[    0.811520] oxnas-dwmac 40400000.ethernet: Got valid mac_adr from cmdline
[    0.818827] oxnas-dwmac 40400000.ethernet:   DWMAC100
[    0.823841] oxnas-dwmac 40400000.ethernet: No HW DMA feature register supported
[    0.831165] oxnas-dwmac 40400000.ethernet: Normal descriptors
[    0.836923] oxnas-dwmac 40400000.ethernet: Ring mode enabled
[    1.483367] oxnas-dwmac 40400000.ethernet: Cannot register the MDIO bus
[    1.490043] oxnas-dwmac 40400000.ethernet: stmmac_dvr_probe: MDIO bus (id: 0) registration failed
[    1.499193] oxnas-dwmac: probe of 40400000.ethernet failed with error -5

After turning on MDIO there is a resulting kernel log:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.15.63 (user@3-rdsgsp) (arm-openwrt-linux-muslgnueabi-gcc (OpenWrt GCC 11.2.0 r19617-4a8eaa5c7c) 11.2.0, GNU ld (GNU Binutils) 2.38) #0 Mon May 9 13:31:01 2022
[    0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=0005317f
[    0.000000] CPU: VIVT data cache, VIVT instruction cache
[    0.000000] OF: fdt: Machine model: Western Digital My Book World Edition
[    0.000000] Memory policy: Data cache writeback
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000048000000-0x000000004fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000048000000-0x000000004fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000048000000-0x000000004fffffff]
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
[    0.000000] Kernel command line: console=ttyS1,115200n8 earlyprintk=serial root=/dev/md0 console=ttyS0,115200 elevator=cfq mac_adr=0x00,0x90,0xA9,0x71,0x14,0x00 mem=128M wixmodel=WXLXN ps
[    0.000000] Kernel parameter elevator= does not have any effect anymore.
[    0.000000] Please use sysfs to set IO scheduler for individual devices.
[    0.000000] Unknown kernel command line parameters "earlyprintk=serial wixmodel=WXLXN poweroutage=yes", will be passed to user space.
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 111804K/131072K available (6144K kernel code, 6561K rwdata, 1148K rodata, 1024K init, 2129K bss, 19268K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] FPGA IRQ chip 0 "interrupt-controller" @ (ptrval), 32 irqs
[    0.000007] sched_clock: 24 bits at 1562kHz, resolution 640ns, wraps every 5368708800ns
[    0.000127] clocksource: oxnas_rps_clocksource_timer: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 4778150833 ns
[    0.000183] timer_oxnas_rps: Registered clocksource rate 1562500Hz
[    0.000232] timer_oxnas_rps: Registered clock event rate 25000000Hz prescaler 0 period 250000
[    0.000787] Console: colour dummy device 80x30
[    0.000943] Calibrating delay loop... 182.68 BogoMIPS (lpj=913408)
[    0.070331] pid_max: default: 32768 minimum: 301
[    0.070840] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.070917] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.072913] CPU: Testing write buffer coherency: ok
[    0.075351] Setting up static identity map for 0x48100000 - 0x4810003c
[    0.083260] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.083355] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[    0.083573] pinctrl core: initialized pinctrl subsystem
[    0.085754] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.087370] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.090679] cpuidle: using governor ladder
[    0.090732] cpuidle: using governor menu
[    0.091167] No ATAGs?
[    0.126481] SCSI subsystem initialized
[    0.127651] usbcore: registered new interface driver usbfs
[    0.127814] usbcore: registered new interface driver hub
[    0.127959] usbcore: registered new device driver usb
[    0.130629] clocksource: Switched to clocksource oxnas_rps_clocksource_timer
[    0.139276] NET: Registered PF_INET protocol family
[    0.139852] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    0.141417] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[    0.141541] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.141617] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.141697] TCP bind hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.141766] TCP: Hash tables configured (established 1024 bind 1024)
[    0.141983] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
[    0.142073] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
[    0.142676] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.145025] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[    0.163472] SGI XFS with security attributes, no debug enabled
[    0.172419] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.174624] printk: console [ttyS1] disabled
[    0.174968] 44300000.serial: ttyS1 at MMIO 0x44300000 (irq = 40, base_baud = 11458333) is a 16550A
[    0.598691] printk: console [ttyS1] enabled
[    0.613820] loop: module loaded
[    0.617781] oxnas-sata: waiting for DMA to initialize
[    0.625770] oxnas-dwmac 40400000.ethernet: IRQ eth_wake_irq not found
[    0.632270] oxnas-dwmac 40400000.ethernet: IRQ eth_lpi not found
[    0.638563] oxnas-dwmac 40400000.ethernet: PTP uses main clock
[    0.821523] oxnas-dwmac 40400000.ethernet: Got valid mac_adr from cmdline
[    0.828817] oxnas-dwmac 40400000.ethernet: User ID: 0x11, Synopsys ID: 0x33
[    0.835846] oxnas-dwmac 40400000.ethernet:   DWMAC1000
[    0.840919] oxnas-dwmac 40400000.ethernet: No HW DMA feature register supported
[    0.848242] oxnas-dwmac 40400000.ethernet: Wake-Up On Lan supported
[    0.854520] oxnas-dwmac 40400000.ethernet: Normal descriptors
[    0.860279] oxnas-dwmac 40400000.ethernet: Ring mode enabled
[   45.113251] ET1011C stmmac-0:01: attached PHY driver (mii_bus:phy_addr=stmmac-0:01, irq=POLL)
[   45.124327] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[   45.133029] ledtrig-cpu: registered to indicate activity on CPUs
[   45.140976] NET: Registered PF_INET6 protocol family
[   45.150877] Segment Routing with IPv6
[   45.154765] In-situ OAM (IOAM) with IPv6
[   45.158944] NET: Registered PF_PACKET protocol family
[   45.169441] zswap: loaded using pool zstd/zsmalloc
[   46.457344] oxnas-dma 45600000.dma: OXNAS DMA Registered
[   46.518343] oxnas-sata: 934 two-ports SATA core v1.F2 (0x07F20008), iomap=[0xC9800000-0xC98FFFFF]
[   46.531645] scsi host0: oxnas-sata
[   46.536612] scsi host1: oxnas-sata
[   46.540510] ata1: SATA max UDMA/133 irq 34
[   46.544648] ata2: SATA max UDMA/133 irq 34
[   48.468719] ata1: SATA link down (SStatus 0 SControl 300)
[   50.633493] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[   50.692995] ata2.00: ATA-9: WDC WD5000LPCX-24C6HT0, 02.01A02, max UDMA/133
[   50.699933] ata2.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 0/32)
[   50.707584] ata2.00: configured for UDMA/133
[   50.712901] scsi 1:0:0:0: Direct-Access     ATA      WDC WD5000LPCX-2 1A02 PQ: 0 ANSI: 5
[   50.724484] sd 1:0:0:0: [sda] 976773168 512-byte logical blocks: (500 GB/466 GiB)
[   50.732020] sd 1:0:0:0: [sda] 4096-byte physical blocks
[   50.737503] sd 1:0:0:0: [sda] Write Protect is off
[   50.742817] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[   51.339015]  sda: sda1 sda2
[   51.345219] sd 1:0:0:0: [sda] Attached SCSI disk
[   51.350040] md: Waiting for all devices to be available before autodetect
[   51.356848] md: If you don't use raid, use raid=noautodetect
[   51.362516] md: Autodetecting RAID arrays.
[   51.394887] md: invalid raid superblock magic on sda2
[   51.399982] md: sda2 does not have a valid v0.90 superblock, not importing!
[   51.406979] md: autorun ...
[   51.411180] md: running: <sda1>
[   51.416497] md/raid1:md0: active with 1 out of 2 mirrors
[   51.422018] md0: detected capacity change from 0 to 5359488
[   51.427699] md: ... autorun DONE.
[   51.439366] EXT4-fs (md0): mounting ext3 file system using the ext4 subsystem
[   51.450725] EXT4-fs (md0): INFO: recovery required on readonly filesystem
[   51.457562] EXT4-fs (md0): write access will be enabled during recovery
[  361.867166] random: crng init done

And that's it. No matter ethernet cable is plugged in or not. Also earlier I tried all manipulations with 5.10 - result is almost the same.

What am I doing wrong?
Thanks!
@Ykidia
Copy link
Author

Ykidia commented Aug 27, 2022 •
edited
Loading

P.S.

[    0.821523] oxnas-dwmac 40400000.ethernet: Got valid mac_adr from cmdline

goes from my patch to get MAC address from kernel command line as in original NAS (see log).
Here are the patch contents:

--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
@@ -54,6 +54,25 @@
 	struct regmap	*regmap;
 };
 
+/* Ethernet MAC adr to assign to interface */
+static u8 mac_adr[ETH_ALEN] = {0};
+
+static int __init set_mac_adr(char *addr)
+{
+	const int eth_sz = ETH_ALEN + 1;
+	int eth_octets[eth_sz], i = 1;
+	if (get_options(addr, eth_sz, eth_octets)) {
+		while (i <= eth_octets[0]) {
+			mac_adr[i - 1] = eth_octets[i];
+			if (++i >= eth_sz)
+				break;
+		}
+		return 1;
+	}
+	return 0;
+}
+__setup("mac_adr=", set_mac_adr);
+
 static int oxnas_dwmac_init(struct platform_device *pdev, void *priv)
 {
 	struct oxnas_dwmac *dwmac = priv;
@@ -112,7 +141,7 @@
 	struct plat_stmmacenet_data *plat_dat;
 	struct stmmac_resources stmmac_res;
 	struct oxnas_dwmac *dwmac;
-	int ret;
+	int i, ret;
 
 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 	if (ret)
@@ -155,6 +185,13 @@
 	ret = oxnas_dwmac_init(pdev, plat_dat->bsp_priv);
 	if (ret)
 		goto err_remove_config_dt;
+
+	if (is_valid_ether_addr(mac_adr)) {
+		dev_info(&pdev->dev, "Got valid mac_adr from cmdline\n");
+		for (i = 0; i < ETH_ALEN; i++) {
+			stmmac_res.mac[i] = (unsigned char)mac_adr[i];
+		}
+	}
 
 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 	if (ret)

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@Ykidia