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fixup
1 parent 103acf2 commit ba916ae

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5 files changed

+16
-8
lines changed

5 files changed

+16
-8
lines changed

core/kt-osrd-rjs-parser/src/main/kotlin/fr/sncf/osrd/RawInfraRJSParser.kt

+1-1
Original file line numberDiff line numberDiff line change
@@ -418,7 +418,7 @@ fun parseRjsElectrification(
418418
previousElectrification.value != electrification.voltage &&
419419
previousElectrification.value != ""
420420
) {
421-
electrificationConflictAggregator.logError(
421+
electrificationConflictAggregator.registerError(
422422
"Electrification conflict on track-range ${electrificationRange.trackSectionID}" +
423423
"[${previousElectrification.lower + chunk.offset.distance}, " +
424424
"${previousElectrification.upper + chunk.offset.distance}]: " +

core/kt-osrd-signaling/src/main/kotlin/fr/sncf/osrd/signaling/impl/BlockBuilder.kt

+1-1
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ private fun getInitPartialBlocks(
218218
val isBufferStop = rawSignalingInfra.isBufferStop(entryDet.value)
219219
if (entrySignals == null) {
220220
if (!isBufferStop)
221-
missingSignalLogAggregator.logError(
221+
missingSignalLogAggregator.registerError(
222222
"no signal at non buffer stop ${rawSignalingInfra.getDetectorName(entryDet.value)}:${entryDet.direction}"
223223
)
224224
initialBlocks.add(

core/kt-osrd-signaling/src/main/kotlin/fr/sncf/osrd/signaling/impl/SignalingSimulatorImpl.kt

+2-2
Original file line numberDiff line numberDiff line change
@@ -122,14 +122,14 @@ class SignalingSimulatorImpl(override val sigModuleManager: SigSystemManager) :
122122
val entrySignal = rawSignalingInfra.getLogicalSignalName(signals[0])
123123
val exitSignal =
124124
rawSignalingInfra.getLogicalSignalName(signals[signals.size - 1])
125-
blockLogAggregator.logError(
125+
blockLogAggregator.registerError(
126126
"error in block from $entrySignal to $exitSignal: $errorType"
127127
)
128128
}
129129

130130
override fun reportSignal(sigIndex: Int, errorType: String) {
131131
val signal = rawSignalingInfra.getLogicalSignalName(signals[sigIndex])
132-
signalLogAggregator.logError("error at signal $signal: $errorType")
132+
signalLogAggregator.registerError("error at signal $signal: $errorType")
133133
}
134134
}
135135
sigModuleManager.checkSignalingSystemBlock(reporter, sigSystem, sigBlock)

core/kt-osrd-utils/src/main/kotlin/fr/sncf/osrd/utils/LogAggregator.kt

+1-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ data class LogAggregator(
1818
private var savedErrors = mutableListOf<String>()
1919

2020
/** Registers an error. Does not log anything before the `reportSummary` call. */
21-
fun logError(msg: String) {
21+
fun registerError(msg: String) {
2222
nErrors++
2323
if (savedErrors.size < maxReportedErrors) savedErrors.add(msg)
2424
}

core/src/main/kotlin/fr/sncf/osrd/api/api_v2/RequirementsParser.kt

+11-3
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ import fr.sncf.osrd.api.api_v2.conflicts.WorkSchedulesRequest
55
import fr.sncf.osrd.conflicts.*
66
import fr.sncf.osrd.sim_infra.api.RawSignalingInfra
77
import fr.sncf.osrd.standalone_sim.result.ResultTrain
8+
import fr.sncf.osrd.utils.LogAggregator
89
import fr.sncf.osrd.utils.units.Duration
910
import fr.sncf.osrd.utils.units.TimeDelta
1011
import fr.sncf.osrd.utils.units.seconds
@@ -99,9 +100,12 @@ fun convertWorkScheduleMap(
99100
timeToAdd: TimeDelta = 0.seconds
100101
): Collection<Requirements> {
101102
val res = mutableListOf<Requirements>()
103+
val logAggregator = LogAggregator({ requirementsParserLogger.warn(it) })
102104
for (entry in workSchedules) {
103105
val workScheduleRequirements = mutableListOf<ResultTrain.SpacingRequirement>()
104-
workScheduleRequirements.addAll(convertWorkSchedule(rawInfra, entry.value, timeToAdd))
106+
workScheduleRequirements.addAll(
107+
convertWorkSchedule(rawInfra, entry.value, timeToAdd, logAggregator)
108+
)
105109
res.add(
106110
Requirements(
107111
RequirementId(entry.key, RequirementType.WORK_SCHEDULE),
@@ -122,9 +126,12 @@ fun convertWorkScheduleCollection(
122126
workSchedules: Collection<WorkSchedule>,
123127
timeToAdd: TimeDelta = 0.seconds,
124128
): Requirements {
129+
val logAggregator = LogAggregator({ requirementsParserLogger.warn(it) })
125130
val workSchedulesRequirements = mutableListOf<ResultTrain.SpacingRequirement>()
126131
for (workSchedule in workSchedules) {
127-
workSchedulesRequirements.addAll(convertWorkSchedule(rawInfra, workSchedule, timeToAdd))
132+
workSchedulesRequirements.addAll(
133+
convertWorkSchedule(rawInfra, workSchedule, timeToAdd, logAggregator)
134+
)
128135
}
129136
return Requirements(
130137
RequirementId(DEFAULT_WORK_SCHEDULE_ID, RequirementType.WORK_SCHEDULE),
@@ -137,6 +144,7 @@ private fun convertWorkSchedule(
137144
rawInfra: RawSignalingInfra,
138145
workSchedule: WorkSchedule,
139146
timeToAdd: TimeDelta = 0.seconds,
147+
logAggregator: LogAggregator,
140148
): Collection<ResultTrain.SpacingRequirement> {
141149
val res = mutableListOf<ResultTrain.SpacingRequirement>()
142150

@@ -181,7 +189,7 @@ private fun convertWorkSchedule(
181189
"${tracksNotCoveredByRoutes.size} track sections were not fully covered by routes (ignoring some work schedules): " +
182190
tracksNotCoveredByRoutes.take(3).joinToString(", ") +
183191
(if (tracksNotCoveredByRoutes.size > 3) ", ..." else "")
184-
requirementsParserLogger.warn(msg)
192+
logAggregator.registerError(msg)
185193
}
186194
return res
187195
}

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