Skip to content

issues Search Results · repo:OpenTimer/Parser-Verilog language:Verilog

Filter by

8 results
 (74 ms)

8 results

inOpenTimer/Parser-Verilog (press backspace or delete to remove)

OpenTimer/Parser-Verilog
Got syntax error on using '&' or '~'

module and_gate ( input a, input b, output out ); assign out = a b; endmodule
  • Rafayelyan
  • Opened 
    on Mar 19, 2024
  • #15

OpenTimer/Parser-Verilog
Build error

Hi, I am trying to build Parser-Verilog on my ubuntu system. I am getting the following error from make command. /usr/bin/cmake -H/home/ ... /Parser-Verilog -B/home/ ... /Parser-Verilog/build --check-build-system ...
  • Siddhartha123
  • Opened 
    on Jun 27, 2023
  • #14

OpenTimer/Parser-Verilog
escaped name that ends at end of line fails

If I have this structure, where the escaped name is the last item on the line. wire \n_12 , \n_13 , \n_14 , \n_15 ; I will get: Failed to match : Parser error: syntax error, unexpected end of file, expecting ...
  • sjs-dogsrule
  • Opened 
    on Oct 5, 2022
  • #13

OpenTimer/Parser-Verilog
Publish to conan

Hi, Would it be possible to publish the code to conan ? I have tried modifying it to be publishable, but my conan-fu is miserable ...
  • bestouff
  • 1
  • Opened 
    on Mar 31, 2022
  • #10

OpenTimer/Parser-Verilog
Do parser-verilog support behavorial-level RTL code?

It seems that the parse only support netlist level verilog code? Does it support behavorial level verilog? For example, the reg key word seems not supported yet?
  • hunterzju
  • Opened 
    on Nov 17, 2021
  • #8

OpenTimer/Parser-Verilog
Out Of Tree Build Fails

Hi there, I have cloned your repository, and found that the sequence of commands: git clone https://github.com/OpenTimer/Parser-Verilog.git cd Parser-Verilog mkdir build cd build cmake ../ make Fails ...
  • ngiambla
  • 1
  • Opened 
    on Jun 11, 2019
  • #3

OpenTimer/Parser-Verilog
Parse issues with delimiter.

I ve found out that below wire definition with delimiter generated below problem. Could you fix this issue? For example, below two wire definition generated below logs. wire \fifo_in/enq_i; wire \fifo_in/tail_r; ...
  • mgwoo
  • 6
  • Opened 
    on Jan 8, 2019
  • #2

OpenTimer/Parser-Verilog
Compile Issues

Thanks for really great work! I ve found two compile issues regarding with this Verilog parser. 1) Flex 2.5.37 is compile-able, but flex 2.6.4 generated compile error. Below command, $ flex ...
  • mgwoo
  • 4
  • Opened 
    on Jan 8, 2019
  • #1
Issue origami icon

Learn how you can use GitHub Issues to plan and track your work.

Save views for sprints, backlogs, teams, or releases. Rank, sort, and filter issues to suit the occasion. The possibilities are endless.Learn more about GitHub Issues
ProTip! 
Restrict your search to the title by using the in:title qualifier.
Issue origami icon

Learn how you can use GitHub Issues to plan and track your work.

Save views for sprints, backlogs, teams, or releases. Rank, sort, and filter issues to suit the occasion. The possibilities are endless.Learn more about GitHub Issues
ProTip! 
Restrict your search to the title by using the in:title qualifier.
Issue search results · GitHub