Skip to content

Commit ec3f189

Browse files
PilnyTomasPilnyTomas
committed
Enumeration fix
1 parent 5c67334 commit ec3f189

File tree

1 file changed

+30
-30
lines changed

1 file changed

+30
-30
lines changed

‎libraries/ESP32/examples/ResetReason/ResetReason.ino‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -34,21 +34,21 @@ void print_reset_reason(RESET_REASON reason)
3434
{
3535
switch ( reason)
3636
{
37-
case 1 : Serial.println ("POWERON_RESET");break; /**<1, Vbat power on reset*/
38-
case 3 : Serial.println ("SW_RESET");break; /**<3, Software reset digital core*/
39-
case 4 : Serial.println ("OWDT_RESET");break; /**<4, Legacy watch dog reset digital core*/
40-
case 5 : Serial.println ("DEEPSLEEP_RESET");break; /**<5, Deep Sleep reset digital core*/
41-
case 6 : Serial.println ("SDIO_RESET");break; /**<6, Reset by SLC module, reset digital core*/
42-
case 7 : Serial.println ("TG0WDT_SYS_RESET");break; /**<7, Timer Group0 Watch dog reset digital core*/
43-
case 8 : Serial.println ("TG1WDT_SYS_RESET");break; /**<8, Timer Group1 Watch dog reset digital core*/
44-
case 9 : Serial.println ("RTCWDT_SYS_RESET");break; /**<9, RTC Watch dog Reset digital core*/
45-
case 10 : Serial.println ("INTRUSION_RESET");break; /**<10, Instrusion tested to reset CPU*/
46-
case 11 : Serial.println ("TGWDT_CPU_RESET");break; /**<11, Time Group reset CPU*/
47-
case 12 : Serial.println ("SW_CPU_RESET");break; /**<12, Software reset CPU*/
48-
case 13 : Serial.println ("RTCWDT_CPU_RESET");break; /**<13, RTC Watch dog Reset CPU*/
49-
case 14 : Serial.println ("EXT_CPU_RESET");break; /**<14, for APP CPU, reseted by PRO CPU*/
50-
case 15 : Serial.println ("RTCWDT_BROWN_OUT_RESET");break;/**<15, Reset when the vdd voltage is not stable*/
51-
case 16 : Serial.println ("RTCWDT_RTC_RESET");break; /**<16, RTC Watch dog reset digital core and rtc module*/
37+
case POWERON_RESET : Serial.println ("POWERON_RESET");break; /**<1, Vbat power on reset*/
38+
case SW_RESET : Serial.println ("SW_RESET");break; /**<3, Software reset digital core*/
39+
case OWDT_RESET : Serial.println ("OWDT_RESET");break; /**<4, Legacy watch dog reset digital core*/
40+
case DEEPSLEEP_RESET : Serial.println ("DEEPSLEEP_RESET");break; /**<5, Deep Sleep reset digital core*/
41+
case SDIO_RESET : Serial.println ("SDIO_RESET");break; /**<6, Reset by SLC module, reset digital core*/
42+
case TG0WDT_SYS_RESET : Serial.println ("TG0WDT_SYS_RESET");break; /**<7, Timer Group0 Watch dog reset digital core*/
43+
case TG1WDT_SYS_RESET : Serial.println ("TG1WDT_SYS_RESET");break; /**<8, Timer Group1 Watch dog reset digital core*/
44+
case RTCWDT_SYS_RESET : Serial.println ("RTCWDT_SYS_RESET");break; /**<9, RTC Watch dog Reset digital core*/
45+
case INTRUSION_RESET : Serial.println ("INTRUSION_RESET");break; /**<10, Instrusion tested to reset CPU*/
46+
case TGWDT_CPU_RESET : Serial.println ("TGWDT_CPU_RESET");break; /**<11, Time Group reset CPU*/
47+
case SW_CPU_RESET : Serial.println ("SW_CPU_RESET");break; /**<12, Software reset CPU*/
48+
case RTCWDT_CPU_RESET : Serial.println ("RTCWDT_CPU_RESET");break; /**<13, RTC Watch dog Reset CPU*/
49+
case EXT_CPU_RESET : Serial.println ("EXT_CPU_RESET");break; /**<14, for APP CPU, reseted by PRO CPU*/
50+
case RTCWDT_BROWN_OUT_RESET : Serial.println ("RTCWDT_BROWN_OUT_RESET");break; /**<15, Reset when the vdd voltage is not stable*/
51+
case RTCWDT_RTC_RESET : Serial.println ("RTCWDT_RTC_RESET");break; /**<16, RTC Watch dog reset digital core and rtc module*/
5252
default : Serial.println ("NO_MEAN");
5353
}
5454
}
@@ -57,21 +57,21 @@ void verbose_print_reset_reason(RESET_REASON reason)
5757
{
5858
switch ( reason)
5959
{
60-
case 1 : Serial.println ("Vbat power on reset");break;
61-
case 3 : Serial.println ("Software reset digital core");break;
62-
case 4 : Serial.println ("Legacy watch dog reset digital core");break;
63-
case 5 : Serial.println ("Deep Sleep reset digital core");break;
64-
case 6 : Serial.println ("Reset by SLC module, reset digital core");break;
65-
case 7 : Serial.println ("Timer Group0 Watch dog reset digital core");break;
66-
case 8 : Serial.println ("Timer Group1 Watch dog reset digital core");break;
67-
case 9 : Serial.println ("RTC Watch dog Reset digital core");break;
68-
case 10 : Serial.println ("Instrusion tested to reset CPU");break;
69-
case 11 : Serial.println ("Time Group reset CPU");break;
70-
case 12 : Serial.println ("Software reset CPU");break;
71-
case 13 : Serial.println ("RTC Watch dog Reset CPU");break;
72-
case 14 : Serial.println ("for APP CPU, reseted by PRO CPU");break;
73-
case 15 : Serial.println ("Reset when the vdd voltage is not stable");break;
74-
case 16 : Serial.println ("RTC Watch dog reset digital core and rtc module");break;
60+
case POWERON_RESET : Serial.println ("Vbat power on reset");break;
61+
case SW_RESET : Serial.println ("Software reset digital core");break;
62+
case OWDT_RESET : Serial.println ("Legacy watch dog reset digital core");break;
63+
case DEEPSLEEP_RESET : Serial.println ("Deep Sleep reset digital core");break;
64+
case SDIO_RESET : Serial.println ("Reset by SLC module, reset digital core");break;
65+
case TG0WDT_SYS_RESET : Serial.println ("Timer Group0 Watch dog reset digital core");break;
66+
case TG1WDT_SYS_RESET : Serial.println ("Timer Group1 Watch dog reset digital core");break;
67+
case RTCWDT_SYS_RESET : Serial.println ("RTC Watch dog Reset digital core");break;
68+
case INTRUSION_RESET : Serial.println ("Instrusion tested to reset CPU");break;
69+
case TGWDT_CPU_RESET : Serial.println ("Time Group reset CPU");break;
70+
case SW_CPU_RESET : Serial.println ("Software reset CPU");break;
71+
case RTCWDT_CPU_RESET : Serial.println ("RTC Watch dog Reset CPU");break;
72+
case EXT_CPU_RESET : Serial.println ("for APP CPU, reseted by PRO CPU");break;
73+
case RTCWDT_BROWN_OUT_RESET : Serial.println ("Reset when the vdd voltage is not stable");break;
74+
case RTCWDT_RTC_RESET : Serial.println ("RTC Watch dog reset digital core and rtc module");break;
7575
default : Serial.println ("NO_MEAN");
7676
}
7777
}

0 commit comments

Comments
 (0)