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fpu.core
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CAPI=2:
name: socet:aft:fpu:0.1.0
description: SoCET FPU module
filesets:
rtl:
# depend:
# - "socet:digital-lib:counter"
files:
- src/fpu.sv
file_type: systemVerilogSource
tb:
files:
- tb/tb_fpu.sv
file_type: systemVerilogSource
rtl_multiply:
# depend:
# - "socet:digital-lib:counter"
# - "socet:digital-lib:shift_register"
# - "socet:digital-lib:edge_detector"
files:
- include/fpu_types_pkg.vh : {is_include_file: true}
- include/fpu_types_pkg.vh : {is_include_file: true}
- src/half_precision/multiplication/float_mult_16bit.sv
file_type: systemVerilogSource
tb_multiply:
files:
- include/fpu_types_pkg.vh : {is_include_file: true}
- src/half_precision/multiplication/tb_multiply.sv
file_type: systemVerilogSource
rtl_add:
# depend:
# - "socet:digital-lib:counter"
# - "socet:digital-lib:shift_register"
# - "socet:digital-lib:edge_detector"
files:
- include/fpu_types_pkg.vh : {is_include_file: true}
- src/half_precision/addition/float_add.sv
file_type: systemVerilogSource
tb_add_16bit:
files:
- include/fpu_types_pkg.vh : {is_include_file: true}
- src/half_precision/addition/tb_add_16bit.sv
file_type: systemVerilogSource
targets:
default: &default
filesets:
- rtl
toplevel: fpu
multiply: &multiply
filesets:
- rtl_multiply
toplevel: multiply
add: &add
filesets:
- rtl_add
toplevel: add
sim:
<<: *default
description: Simulate w/TB
default_tool: xcelium
filesets_append:
- tb
toplevel:
- tb_fpu
tools:
xcelium:
xrun_options:
- +xmtimescale+1ns/100ps
modelsim:
vsim_options:
- -vopt
- -voptargs='+acc'
- -t ps
vcs:
vcs_options:
- -assert svaext
verilator:
verilator_options:
- --trace
- --trace-fst
- --trace-structs
- --timing
- --binary
- --timescale 1ns
sim_multiply:
<<: *multiply
description: Simulate w/TB
default_tool: xcelium
filesets_append:
- tb_multiply
toplevel:
- tb_multiply
tools:
xcelium:
xrun_options:
- +xmtimescale+1ns/100ps
modelsim:
vsim_options:
- -vopt
- -voptargs='+acc'
- -t ps
vcs:
vcs_options:
- -assert svaext
verilator:
verilator_options:
- --trace
- --trace-fst
- --trace-structs
- --timing
- --binary
- --timescale 1ns
sim_add:
<<: *add
description: Simulate w/TB
default_tool: xcelium
filesets_append:
- tb_add_16bit
toplevel:
- tb_add_16bit
tools:
xcelium:
xrun_options:
- +xmtimescale+1ns/100ps
modelsim:
vsim_options:
- -vopt
- -voptargs='+acc'
- -t ps
vcs:
vcs_options:
- -assert svaext
verilator:
verilator_options:
- --trace
- --trace-fst
- --trace-structs
- --timing
- --binary
- --timescale 1ns
fpga:
<<: *default
description: Synthesize for FPGA
default_tool: quartus
toplevel:
- fpu
parameters:
- SYNTHESIS=true
tools:
quartus:
family: Cyclone IV E
device: EP4CE115F29C7
lint:
filesets:
- lint_files
description: Linting
default_tool: veriblelint
toplevel: tb_fpu
tools:
veriblelint:
verible_lint_args: ['--autofix=inplace-interactive', '--rules_config_search']
format:
filesets:
- lint_files
description: Formatting
default_tool: veribleformat
toplevel: tb_fpu
tools:
veribleformat:
verible_format_args: ['--indentation_spaces=4', '--inplace']
parameters:
SYNTHESIS:
datatype: bool
paramtype: vlogdefine