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QPY fails to load a circuit that has registers, but bit index 0 isn't in a register or at least, isn't in the circuit by the time a later register is read.
TypeError Traceback (most recent call last)
<ipython-input-1-ddaf374c6759> in <module>
11 dump(qc, f)
12 f.seek(0)
---> 13 out, = load(f)
14
~/code/qiskit/terra/qiskit/qpy/interface.py in load(file_obj, metadata_deserializer)
269 for _ in range(data.num_programs):
270 programs.append(
--> 271 loader(file_obj, data.qpy_version, metadata_deserializer=metadata_deserializer)
272 )
273 return programs
~/code/qiskit/terra/qiskit/qpy/binary_io/circuits.py in read_circuit(file_obj, version, metadata_deserializer)
924 if start > len(circ.qubits):
925 bits = [bit_type() for _ in range(start - bit_len)]
--> 926 circ.add_bits(bit_len)
927 if in_circuit:
928 circ.add_register(reg)
~/code/qiskit/terra/qiskit/circuit/quantumcircuit.py in add_bits(self, bits)
1394 def add_bits(self, bits: Iterable[Bit]) -> None:
1395 """Add Bits to the circuit."""
-> 1396 duplicate_bits = set(self._qubit_indices).union(self._clbit_indices).intersection(bits)
1397 if duplicate_bits:
1398 raise CircuitError(f"Attempted to add bits found already in circuit: {duplicate_bits}")
TypeError: 'int' object is not iterable
What should happen?
Correct load from QPY.
Any suggestions?
qpy/binary_io/circuits.py:926 is obviously wrong: it's passing an int to QuantumCircuit.add_bits rather than the bits that it has defined right above. This isn't the only issue, though - the whole register reconstruction has an incorrect model of bit ownership and bit ordering, so a more complete example like
Environment
What is happening?
QPY fails to load a circuit that has registers, but bit index 0 isn't in a register or at least, isn't in the circuit by the time a later register is read.
How can we reproduce the issue?
fails with
What should happen?
Correct load from QPY.
Any suggestions?
qpy/binary_io/circuits.py:926
is obviously wrong: it's passing anint
toQuantumCircuit.add_bits
rather than thebits
that it has defined right above. This isn't the only issue, though - the whole register reconstruction has an incorrect model of bit ownership and bit ordering, so a more complete example likefails, because in the output circuit, the clbits go
[('c1', 0), ('c1', 1), Clbit()]
, whereas they should be[Clbit(), ('c1', 0), ('c1', 1)]
.The text was updated successfully, but these errors were encountered: