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1 | 1 | /* |
2 | | - * Copyright (C) 2016 Freie Universität Berlin |
3 | | - * 2017 Inria |
| 2 | + * Copyright (C) 2017 Inria |
4 | 3 | * |
5 | 4 | * This file is subject to the terms and conditions of the GNU Lesser |
6 | 5 | * General Public License v2.1. See the file LICENSE in the top level |
|
14 | 13 | * @file |
15 | 14 | * @brief Configuration of CPU peripherals for Arduino MKRZERO board |
16 | 15 | * |
17 | | - * @author Thomas Eichinger <thomas.eichinger@fu-berlin.de> |
18 | | - * @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
19 | | - * @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de> |
20 | 16 | * @author Alexandre Abadie <alexandre.abadie@inria.fr> |
21 | 17 | */ |
22 | 18 |
|
23 | 19 | #ifndef PERIPH_CONF_H |
24 | 20 | #define PERIPH_CONF_H |
25 | 21 |
|
26 | | -#include <stdint.h> |
27 | | - |
28 | | -#include "cpu.h" |
29 | 22 | #include "periph_cpu.h" |
| 23 | +#include "periph_conf_common.h" |
30 | 24 |
|
31 | 25 | #ifdef __cplusplus |
32 | 26 | extern "C" { |
33 | 27 | #endif |
34 | 28 |
|
35 | | -/** |
36 | | - * @brief External oscillator and clock configuration |
37 | | - * |
38 | | - * For selection of the used CORECLOCK, we have implemented two choices: |
39 | | - * |
40 | | - * - usage of the PLL fed by the internal 8MHz oscillator divided by 8 |
41 | | - * - usage of the internal 8MHz oscillator directly, divided by N if needed |
42 | | - * |
43 | | - * |
44 | | - * The PLL option allows for the usage of a wider frequency range and a more |
45 | | - * stable clock with less jitter. This is why we use this option as default. |
46 | | - * |
47 | | - * The target frequency is computed from the PLL multiplier and the PLL divisor. |
48 | | - * Use the following formula to compute your values: |
49 | | - * |
50 | | - * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV |
51 | | - * |
52 | | - * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL |
53 | | - * frequency is 96MHz. So PLL_MULL must be between 31 and 95! |
54 | | - * |
55 | | - * |
56 | | - * The internal Oscillator used directly can lead to a slightly better power |
57 | | - * efficiency to the cost of a less stable clock. Use this option when you know |
58 | | - * what you are doing! The actual core frequency is adjusted as follows: |
59 | | - * |
60 | | - * CORECLOCK = 8MHz / DIV |
61 | | - * |
62 | | - * NOTE: A core clock frequency below 1MHz is not recommended |
63 | | - * |
64 | | - * @{ |
65 | | - */ |
66 | | -#define CLOCK_USE_PLL (1) |
67 | | - |
68 | | -#if CLOCK_USE_PLL |
69 | | -/* edit these values to adjust the PLL output frequency */ |
70 | | -#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */ |
71 | | -#define CLOCK_PLL_DIV (1U) /* adjust to your needs */ |
72 | | -/* generate the actual used core clock frequency */ |
73 | | -#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV) |
74 | | -#else |
75 | | -/* edit this value to your needs */ |
76 | | -#define CLOCK_DIV (1U) |
77 | | -/* generate the actual core clock frequency */ |
78 | | -#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV) |
79 | | -#endif |
80 | | -/** @} */ |
81 | | - |
82 | | -/** |
83 | | - * @name Timer peripheral configuration |
84 | | - * @{ |
85 | | - */ |
86 | | -#define TIMER_NUMOF (2U) |
87 | | -#define TIMER_0_EN 1 |
88 | | -#define TIMER_1_EN 1 |
89 | | - |
90 | | -/* Timer 0 configuration */ |
91 | | -#define TIMER_0_DEV TC3->COUNT16 |
92 | | -#define TIMER_0_CHANNELS 2 |
93 | | -#define TIMER_0_MAX_VALUE (0xffff) |
94 | | -#define TIMER_0_ISR isr_tc3 |
95 | | - |
96 | | -/* Timer 1 configuration */ |
97 | | -#define TIMER_1_DEV TC4->COUNT32 |
98 | | -#define TIMER_1_CHANNELS 2 |
99 | | -#define TIMER_1_MAX_VALUE (0xffffffff) |
100 | | -#define TIMER_1_ISR isr_tc4 |
101 | | - |
102 | | -/** @} */ |
103 | | - |
104 | | -/** |
105 | | - * @name UART configuration |
106 | | - * @{ |
107 | | - */ |
108 | | -static const uart_conf_t uart_config[] = { |
109 | | - { |
110 | | - .dev = &SERCOM5->USART, |
111 | | - .rx_pin = GPIO_PIN(PB,23), |
112 | | - .tx_pin = GPIO_PIN(PB,22), |
113 | | - .mux = GPIO_MUX_D, |
114 | | - .rx_pad = UART_PAD_RX_3, |
115 | | - .tx_pad = UART_PAD_TX_2 |
116 | | - } |
117 | | -}; |
118 | | - |
119 | | -/* interrupt function name mapping */ |
120 | | -#define UART_0_ISR isr_sercom5 |
121 | | - |
122 | | -#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) |
123 | | -/** @} */ |
124 | | - |
125 | | -/** |
126 | | - * @name PWM configuration |
127 | | - * @{ |
128 | | - */ |
129 | | -#define PWM_0_EN 1 |
130 | | -#define PWM_1_EN 1 |
131 | | -#define PWM_MAX_CHANNELS 2 |
132 | | -/* for compatibility with test application */ |
133 | | -#define PWM_0_CHANNELS PWM_MAX_CHANNELS |
134 | | -#define PWM_1_CHANNELS PWM_MAX_CHANNELS |
135 | | - |
136 | | -/* PWM device configuration */ |
137 | | -static const pwm_conf_t pwm_config[] = { |
138 | | -#if PWM_0_EN |
139 | | - {TCC0, { |
140 | | - /* GPIO pin, MUX value, TCC channel */ |
141 | | - { GPIO_PIN(PA, 8), GPIO_MUX_E, 0 }, |
142 | | - { GPIO_PIN(PA, 9), GPIO_MUX_E, 1 }, |
143 | | - }}, |
144 | | -#endif |
145 | | -#if PWM_1_EN |
146 | | - {TCC1, { |
147 | | - /* GPIO pin, MUX value, TCC channel */ |
148 | | - { GPIO_PIN(PA, 6), GPIO_MUX_E, 0 }, |
149 | | - { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 }, |
150 | | - }}, |
151 | | -#endif |
152 | | -}; |
153 | | - |
154 | | -/* number of devices that are actually defined */ |
155 | | -#define PWM_NUMOF (2U) |
156 | | -/** @} */ |
157 | | - |
158 | | -/** |
159 | | - * @name ADC configuration |
160 | | - * @{ |
161 | | - */ |
162 | | -#define ADC_CONFIG { \ |
163 | | - { GPIO_PIN(PA, 2), 0, 0 }, \ |
164 | | - { GPIO_PIN(PB, 2), 0, 2 }, \ |
165 | | - { GPIO_PIN(PB, 3), 0, 3 }, \ |
166 | | - { GPIO_PIN(PA, 4), 0, 4 }, \ |
167 | | - { GPIO_PIN(PA, 5), 0, 5 }, \ |
168 | | - { GPIO_PIN(PA, 6), 0, 10 }, \ |
169 | | - { GPIO_PIN(PA, 7), 0, 10 }} |
170 | | - |
171 | | -#define ADC_NUMOF (6) |
172 | | -/** @} */ |
173 | | - |
174 | | -/** |
175 | | - * @name SPI configuration |
176 | | - * @{ |
177 | | - */ |
178 | | -static const spi_conf_t spi_config[] = { |
179 | | - { |
180 | | - .dev = &SERCOM1->SPI, |
181 | | - .miso_pin = GPIO_PIN(PA, 19), |
182 | | - .mosi_pin = GPIO_PIN(PB, 16), |
183 | | - .clk_pin = GPIO_PIN(PB, 17), |
184 | | - .miso_mux = GPIO_MUX_D, |
185 | | - .mosi_mux = GPIO_MUX_D, |
186 | | - .clk_mux = GPIO_MUX_D, |
187 | | - .miso_pad = SPI_PAD_MISO_3, |
188 | | - .mosi_pad = SPI_PAD_MOSI_0_SCK_1 |
189 | | - }, |
190 | | - { |
191 | | - .dev = &SERCOM2->SPI, |
192 | | - .miso_pin = GPIO_PIN(PA, 15), |
193 | | - .mosi_pin = GPIO_PIN(PA, 12), |
194 | | - .clk_pin = GPIO_PIN(PA, 13), |
195 | | - .miso_mux = GPIO_MUX_D, |
196 | | - .mosi_mux = GPIO_MUX_D, |
197 | | - .clk_mux = GPIO_MUX_D, |
198 | | - .miso_pad = SPI_PAD_MISO_3, |
199 | | - .mosi_pad = SPI_PAD_MOSI_2_SCK_3 |
200 | | - } |
201 | | -}; |
202 | | - |
203 | | -#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) |
204 | | -/** @} */ |
205 | | - |
206 | | -/** |
207 | | - * @name I2C configuration |
208 | | - * @{ |
209 | | - */ |
210 | | -#define I2C_NUMOF (1U) |
211 | | -#define I2C_0_EN 1 |
212 | | -#define I2C_1_EN 0 |
213 | | -#define I2C_2_EN 0 |
214 | | -#define I2C_3_EN 0 |
215 | | -#define I2C_IRQ_PRIO 1 |
216 | | - |
217 | | -#define I2C_0_DEV SERCOM0->I2CM |
218 | | -#define I2C_0_IRQ SERCOM0_IRQn |
219 | | -#define I2C_0_ISR isr_sercom0 |
220 | | -/* I2C 0 GCLK */ |
221 | | -#define I2C_0_GCLK_ID SERCOM0_GCLK_ID_CORE |
222 | | -#define I2C_0_GCLK_ID_SLOW SERCOM0_GCLK_ID_SLOW |
223 | | -/* I2C 0 pin configuration */ |
224 | | -#define I2C_0_SDA GPIO_PIN(PA, 8) |
225 | | -#define I2C_0_SCL GPIO_PIN(PA, 9) |
226 | | -#define I2C_0_MUX GPIO_MUX_C |
227 | | -/** @} */ |
228 | | - |
229 | 29 | #ifdef __cplusplus |
230 | 30 | } |
231 | 31 | #endif |
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