Addressesd the reviewed feedback in AMDGPUTargetMachine.cpp

Author: vg0204

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -1856,13 +1856,13 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
     // allocations.
     //    addPass(&AMDGPUUpdateAllocatedVGPRLiveRangesID);
 
-    // Now we can perform register-coalescing on remaining copies,
-    // mainly sgpr copies and wwm-vgpr copies.
-    addPass(&RegisterCoalescerID);
-
     // Optimize EXEC-mask related instructions around SGPR register class.
     if (OptExecMaskPreRA)
       addPass(&SIOptimizeExecMaskingPreRAID);
+
+    // Now we can perform register-coalescing on remaining copies,
+    // mainly sgpr copies and wwm-vgpr copies.
+    addPass(&RegisterCoalescerID);
   }
 
   addPass(createSGPRAllocPass(true));

llvm/test/CodeGen/AMDGPU/WaveTransform/wave-transform-llc-pipeline.ll

@@ -385,9 +385,9 @@
 ; GCN-O3-NEXT:        AMDGPU Control Flow Wave Transform
 ; GCN-O3-NEXT:        Slot index numbering
 ; GCN-O3-NEXT:        Live Interval Analysis
+; GCN-O3-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O3-NEXT:        Machine Natural Loop Construction
 ; GCN-O3-NEXT:        Register Coalescer
-; GCN-O3-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Debug Variable Analysis
 ; GCN-O3-NEXT:        Live Stack Slot Analysis