Skip to content

Commit c18db52

Browse files
vg0204vg0204
committed
Addressed the reviewed changes as much as possible.
1 parent 07e94c4 commit c18db52

File tree

3 files changed

+47
-46
lines changed

3 files changed

+47
-46
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUWaveTransform.cpp‎

Lines changed: 20 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1785,13 +1785,14 @@ void ControlFlowRewriter::prepareWaveCfg() {
17851785
/// manipulation.
17861786
void ControlFlowRewriter::rewrite() {
17871787
GCNLaneMaskAnalysis LMA(Function);
1788+
const AMDGPU::LaneMaskConstants &LMC = LMU.getLaneMaskConsts();
17881789

17891790
Register RegAllOnes;
17901791
auto getAllOnes = [&]() {
17911792
if (!RegAllOnes) {
17921793
RegAllOnes = LMU.createLaneMaskReg();
17931794
BuildMI(Function.front(), Function.front().getFirstTerminator(), {},
1794-
TII.get(LMU.consts().MovOpc), RegAllOnes)
1795+
TII.get(LMC.MovOpc), RegAllOnes)
17951796
.addImm(-1);
17961797
}
17971798
return RegAllOnes;
@@ -1841,12 +1842,12 @@ void ControlFlowRewriter::rewrite() {
18411842
if (!LMA.isSubsetOfExec(CondReg, *Node->Block)) {
18421843
CondReg = LMU.createLaneMaskReg();
18431844
BuildMI(*Node->Block, Node->Block->end(), {},
1844-
TII.get(LMU.consts().AndOpc), CondReg)
1845-
.addReg(LMU.consts().ExecReg)
1845+
TII.get(LMC.AndOpc), CondReg)
1846+
.addReg(LMC.ExecReg)
18461847
.addReg(Info.OrigCondition);
18471848
}
18481849
BuildMI(*Node->Block, Node->Block->end(), {}, TII.get(AMDGPU::COPY),
1849-
LMU.consts().VccReg)
1850+
LMC.VccReg)
18501851
.addReg(CondReg);
18511852

18521853
Opcode = AMDGPU::S_CBRANCH_VCCNZ;
@@ -1924,15 +1925,15 @@ void ControlFlowRewriter::rewrite() {
19241925
if (!LaneOrigin.InvertCondition) {
19251926
BuildMI(*LaneOrigin.Node->Block,
19261927
LaneOrigin.Node->Block->getFirstTerminator(), {},
1927-
TII.get(LMU.consts().CSelectOpc), CondReg)
1928-
.addReg(LMU.consts().ExecReg)
1928+
TII.get(LMC.CSelectOpc), CondReg)
1929+
.addReg(LMC.ExecReg)
19291930
.addImm(0);
19301931
} else {
19311932
BuildMI(*LaneOrigin.Node->Block,
19321933
LaneOrigin.Node->Block->getFirstTerminator(), {},
1933-
TII.get(LMU.consts().CSelectOpc), CondReg)
1934+
TII.get(LMC.CSelectOpc), CondReg)
19341935
.addImm(0)
1935-
.addReg(LMU.consts().ExecReg);
1936+
.addReg(LMC.ExecReg);
19361937
}
19371938
} else {
19381939
CondReg = LaneOrigin.CondReg;
@@ -1941,8 +1942,8 @@ void ControlFlowRewriter::rewrite() {
19411942
CondReg = LMU.createLaneMaskReg();
19421943
BuildMI(*LaneOrigin.Node->Block,
19431944
LaneOrigin.Node->Block->getFirstTerminator(), {},
1944-
TII.get(LMU.consts().AndOpc), CondReg)
1945-
.addReg(LMU.consts().ExecReg)
1945+
TII.get(LMC.AndOpc), CondReg)
1946+
.addReg(LMC.ExecReg)
19461947
.addReg(Prev);
19471948

19481949
RegMap[std::make_pair(LaneOrigin.Node->Block, LaneOrigin.CondReg)]
@@ -1962,7 +1963,7 @@ void ControlFlowRewriter::rewrite() {
19621963
CondReg = LMU.createLaneMaskReg();
19631964
BuildMI(*LaneOrigin.Node->Block,
19641965
LaneOrigin.Node->Block->getFirstTerminator(), {},
1965-
TII.get(LMU.consts().XorOpc), CondReg)
1966+
TII.get(LMC.XorOpc), CondReg)
19661967
.addReg(LaneOrigin.CondReg)
19671968
.addImm(-1);
19681969

@@ -1999,7 +2000,7 @@ void ControlFlowRewriter::rewrite() {
19992000
<< '\n');
20002001

20012002
BuildMI(*OriginNode->Block, OriginNode->Block->end(), {},
2002-
TII.get(LMU.consts().MovTermOpc), LMU.consts().ExecReg)
2003+
TII.get(LMC.MovTermOpc), LMC.ExecReg)
20032004
.addReg(OriginCFGNodeInfo.PrimarySuccessorExec);
20042005
BuildMI(*OriginNode->Block, OriginNode->Block->end(), {},
20052006
TII.get(AMDGPU::SI_WAVE_CF_EDGE));
@@ -2046,12 +2047,12 @@ void ControlFlowRewriter::rewrite() {
20462047
Register Rejoin;
20472048

20482049
if (PrimaryExecDef->getParent() == Pred->Block &&
2049-
PrimaryExecDef->getOpcode() == LMU.consts().XorOpc &&
2050+
PrimaryExecDef->getOpcode() == LMC.XorOpc &&
20502051
PrimaryExecDef->getOperand(1).isReg() &&
20512052
PrimaryExecDef->getOperand(2).isReg()) {
2052-
if (PrimaryExecDef->getOperand(1).getReg() == LMU.consts().ExecReg)
2053+
if (PrimaryExecDef->getOperand(1).getReg() == LMC.ExecReg)
20532054
Rejoin = PrimaryExecDef->getOperand(2).getReg();
2054-
else if (PrimaryExecDef->getOperand(2).getReg() == LMU.consts().ExecReg)
2055+
else if (PrimaryExecDef->getOperand(2).getReg() == LMC.ExecReg)
20552056
Rejoin = PrimaryExecDef->getOperand(1).getReg();
20562057
}
20572058

@@ -2069,8 +2070,8 @@ void ControlFlowRewriter::rewrite() {
20692070
if (!Rejoin) {
20702071
Rejoin = LMU.createLaneMaskReg();
20712072
BuildMI(*Pred->Block, Pred->Block->getFirstTerminator(), {},
2072-
TII.get(LMU.consts().XorOpc), Rejoin)
2073-
.addReg(LMU.consts().ExecReg)
2073+
TII.get(LMC.XorOpc), Rejoin)
2074+
.addReg(LMC.ExecReg)
20742075
.addReg(PrimaryExec);
20752076
}
20762077

@@ -2084,8 +2085,8 @@ void ControlFlowRewriter::rewrite() {
20842085

20852086
Register Rejoin = Updater.getValueInMiddleOfBlock(*Secondary->Block);
20862087
BuildMI(*Secondary->Block, Secondary->Block->getFirstNonPHI(), {},
2087-
TII.get(LMU.consts().OrOpc), LMU.consts().ExecReg)
2088-
.addReg(LMU.consts().ExecReg)
2088+
TII.get(LMC.OrOpc), LMC.ExecReg)
2089+
.addReg(LMC.ExecReg)
20892090
.addReg(Rejoin);
20902091

20912092
LLVM_DEBUG(Function.dump());

‎llvm/lib/Target/AMDGPU/GCNLaneMaskUtils.cpp‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ bool GCNLaneMaskUtils::isConstantLaneMask(Register Reg, bool &Val) const {
6363
return false;
6464
}
6565

66-
if (MI->getOpcode() != Constants->MovOpc)
66+
if (MI->getOpcode() != LMC->MovOpc)
6767
return false;
6868

6969
if (!MI->getOperand(1).isImm())
@@ -85,7 +85,7 @@ bool GCNLaneMaskUtils::isConstantLaneMask(Register Reg, bool &Val) const {
8585
/// Create a virtual lanemask register.
8686
Register GCNLaneMaskUtils::createLaneMaskReg() const {
8787
MachineRegisterInfo &MRI = MF->getRegInfo();
88-
return MRI.createVirtualRegister(Constants->SRegClass);
88+
return MRI.createVirtualRegister(LMC->SRegClass);
8989
}
9090

9191
/// Insert the moral equivalent of
@@ -128,10 +128,10 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB,
128128
} else if (CurVal) {
129129
// If PrevReg is undef, prefer to propagate a full constant.
130130
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
131-
.addReg(PrevReg ? Constants->ExecReg : CurReg);
131+
.addReg(PrevReg ? LMC->ExecReg : CurReg);
132132
} else {
133-
BuildMI(MBB, I, DL, TII->get(Constants->XorOpc), DstReg)
134-
.addReg(Constants->ExecReg)
133+
BuildMI(MBB, I, DL, TII->get(LMC->XorOpc), DstReg)
134+
.addReg(LMC->ExecReg)
135135
.addImm(-1);
136136
}
137137
return;
@@ -147,9 +147,9 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB,
147147
} else {
148148
PrevMaskedReg = createLaneMaskReg();
149149
PrevMaskedBuilt =
150-
BuildMI(MBB, I, DL, TII->get(Constants->AndN2Opc), PrevMaskedReg)
150+
BuildMI(MBB, I, DL, TII->get(LMC->AndN2Opc), PrevMaskedReg)
151151
.addReg(PrevReg)
152-
.addReg(Constants->ExecReg);
152+
.addReg(LMC->ExecReg);
153153
}
154154
}
155155
if (!CurConstant) {
@@ -159,9 +159,9 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB,
159159
} else {
160160
CurMaskedReg = createLaneMaskReg();
161161
CurMaskedBuilt =
162-
BuildMI(MBB, I, DL, TII->get(Constants->AndOpc), CurMaskedReg)
162+
BuildMI(MBB, I, DL, TII->get(LMC->AndOpc), CurMaskedReg)
163163
.addReg(CurReg)
164-
.addReg(Constants->ExecReg);
164+
.addReg(LMC->ExecReg);
165165
}
166166
}
167167

@@ -181,13 +181,13 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB,
181181
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(PrevMaskedReg);
182182
}
183183
} else if (PrevConstant && PrevVal) {
184-
BuildMI(MBB, I, DL, TII->get(Constants->OrN2Opc), DstReg)
184+
BuildMI(MBB, I, DL, TII->get(LMC->OrN2Opc), DstReg)
185185
.addReg(CurMaskedReg)
186-
.addReg(Constants->ExecReg);
186+
.addReg(LMC->ExecReg);
187187
} else {
188-
BuildMI(MBB, I, DL, TII->get(Constants->OrOpc), DstReg)
188+
BuildMI(MBB, I, DL, TII->get(LMC->OrOpc), DstReg)
189189
.addReg(PrevMaskedReg)
190-
.addReg(CurMaskedReg ? CurMaskedReg : Constants->ExecReg);
190+
.addReg(CurMaskedReg ? CurMaskedReg : LMC->ExecReg);
191191
}
192192
}
193193

@@ -202,7 +202,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg,
202202

203203
for (;;) {
204204
if (!Register::isVirtualRegister(Reg)) {
205-
if (Reg == LMU.consts().ExecReg &&
205+
if (Reg == LMU.getLaneMaskConsts().ExecReg &&
206206
(!DefInstr || DefInstr->getParent() == &UseBlock))
207207
return true;
208208
return false;
@@ -214,7 +214,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg,
214214
continue;
215215
}
216216

217-
if (DefInstr->getOpcode() == LMU.consts().MovOpc) {
217+
if (DefInstr->getOpcode() == LMU.getLaneMaskConsts().MovOpc) {
218218
if (DefInstr->getOperand(1).isImm() &&
219219
DefInstr->getOperand(1).getImm() == 0)
220220
return true;
@@ -241,11 +241,11 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg,
241241
if (!RemainingDepth--)
242242
return false;
243243

244-
bool LikeOr = DefInstr->getOpcode() == LMU.consts().OrOpc ||
245-
DefInstr->getOpcode() == LMU.consts().XorOpc ||
246-
DefInstr->getOpcode() == LMU.consts().CSelectOpc;
247-
bool IsAnd = DefInstr->getOpcode() == LMU.consts().AndOpc;
248-
bool IsAndN2 = DefInstr->getOpcode() == LMU.consts().AndN2Opc;
244+
bool LikeOr = DefInstr->getOpcode() == LMU.getLaneMaskConsts().OrOpc ||
245+
DefInstr->getOpcode() == LMU.getLaneMaskConsts().XorOpc ||
246+
DefInstr->getOpcode() == LMU.getLaneMaskConsts().CSelectOpc;
247+
bool IsAnd = DefInstr->getOpcode() == LMU.getLaneMaskConsts().AndOpc;
248+
bool IsAndN2 = DefInstr->getOpcode() == LMU.getLaneMaskConsts().AndN2Opc;
249249
if ((LikeOr || IsAnd || IsAndN2) &&
250250
(DefInstr->getOperand(1).isReg() && DefInstr->getOperand(2).isReg())) {
251251
bool FirstIsSubset = isSubsetOfExec(DefInstr->getOperand(1).getReg(),
@@ -274,7 +274,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg,
274274
void GCNLaneMaskUpdater::init(Register Reg) {
275275
Processed = false;
276276
Blocks.clear();
277-
//SSAUpdater.Initialize(LMU.consts().SRegClass);
277+
//SSAUpdater.Initialize(LMU.getLaneMaskConsts().SRegClass);
278278
SSAUpdater.Initialize(Reg);
279279
}
280280

@@ -424,7 +424,7 @@ void GCNLaneMaskUpdater::process() {
424424
// Prepare an all-zero value for the default and reset in accumulating mode.
425425
if (Accumulating && !ZeroReg) {
426426
ZeroReg = LMU.createLaneMaskReg();
427-
BuildMI(Entry, Entry.getFirstTerminator(), {}, TII->get(LMU.consts().MovOpc),
427+
BuildMI(Entry, Entry.getFirstTerminator(), {}, TII->get(LMU.getLaneMaskConsts().MovOpc),
428428
ZeroReg)
429429
.addImm(0);
430430
}

‎llvm/lib/Target/AMDGPU/GCNLaneMaskUtils.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ class MachineFunction;
3131
class GCNLaneMaskUtils {
3232
private:
3333
MachineFunction *MF = nullptr;
34-
const AMDGPU::LaneMaskConstants *Constants = nullptr;
34+
const AMDGPU::LaneMaskConstants *LMC = nullptr;
3535

3636
public:
3737
static const AMDGPU::LaneMaskConstants &getConsts(MachineFunction &MF);
@@ -42,12 +42,12 @@ class GCNLaneMaskUtils {
4242
MachineFunction *function() const { return MF; }
4343
void setFunction(MachineFunction &Func) {
4444
MF = &Func;
45-
Constants = &getConsts(Func);
45+
LMC = &getConsts(Func);
4646
}
4747

48-
const AMDGPU::LaneMaskConstants &consts() const {
49-
assert(Constants);
50-
return *Constants;
48+
const AMDGPU::LaneMaskConstants &getLaneMaskConsts() const {
49+
assert(LMC);
50+
return *LMC;
5151
}
5252

5353
bool maybeLaneMask(Register Reg) const;

0 commit comments

Comments
 (0)