@@ -23,6 +23,57 @@ extern "C" {
2323
2424#define __STM32_PORT (port ) GPIO##port##_BASE
2525
26+ /**
27+ * @brief Calculates the RT-Thread global pin number from an STM32-specific port and pin.
28+ *
29+ * @details
30+ * This macro provides a vendor-specific way to map a human-readable GPIO port
31+ * (e.g., 'A', 'B') and pin number (0-15) to a single integer value that RT-Thread's
32+ * pin device driver uses to identify a pin globally.
33+ *
34+ * The calculation is based on the memory address offset of the target GPIO port's
35+ * base register relative to GPIOA. It assumes a linear memory map for GPIO ports.
36+ *
37+ * It includes special compile-time handling for different STM32 series, such as the
38+ * STM32MP1, which have a different GPIO memory layout (e.g., 4KB stride between
39+ * port registers) and may include special ports like GPIOZ.
40+ *
41+ * @param[in] PORTx The GPIO port letter (e.g., A, B, C, D). Pass the letter without
42+ * quotes (e.g., A, not 'A').
43+ * @param[in] PIN The pin number within the port (an integer from 0 to 15).
44+ *
45+ * @return
46+ * An `rt_base_t` integer representing the unique pin index for use with RT-Thread
47+ * pin device driver functions (e.g., rt_pin_mode(), rt_pin_write()).
48+ *
49+ * @note
50+ * - **STM32 & RT-Thread Specific:** This macro is highly dependent on the STM32 HAL
51+ * and RT-Thread's pin numbering convention. It relies on underlying HAL macros like
52+ * `__STM32_PORT()` and base address definitions like `GPIOA_BASE`.
53+ * - **Not Portable:** Do not use this macro in code intended to be portable across
54+ * different microcontroller vendors.
55+ * - **Compile-Time Evaluation:** The macro is evaluated entirely at compile time. The
56+ * correct implementation for the target STM32 series is selected via preprocessor
57+ * directives (e.g., `SOC_SERIES_STM32MP1`).
58+ * - **Argument Evaluation:** As this is a preprocessor macro, its arguments are
59+ * substituted directly. Avoid passing expressions with side effects (e.g., `i++`)
60+ * as arguments, as they may be evaluated multiple times.
61+ *
62+ * @see rt_pin_mode()
63+ * @see rt_pin_write()
64+ * @see rt_pin_read()
65+ *
66+ * @code
67+ * // Usage Example 1: Configure pin PD11 as a push-pull output.
68+ * rt_pin_mode(GET_PIN(D, 11), PIN_MODE_OUTPUT);
69+ *
70+ * // Usage Example 2: Write a high logic level to pin PA5.
71+ * rt_pin_write(GET_PIN(A, 5), PIN_HIGH);
72+ *
73+ * // Usage Example 3: Read the logic level from pin PC13.
74+ * int level = rt_pin_read(GET_PIN(C, 13));
75+ * @endcode
76+ */
2677#if defined(SOC_SERIES_STM32MP1 )
2778#define GET_PIN (PORTx ,PIN ) (GPIO##PORTx == GPIOZ) ? (176 + PIN) : ((rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN))
2879#else
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