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©DownSampleMe

An FPGA based Image Down Sampler
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About The Project

This repository includes all the project files related to the development of a Custom processor in Verilog HDL for image downsampling. The project was done by a team of 4 undergraduates at the Department of Electronic and Telecommunication Engineering, University of Moratuwa, Sri Lanka. It was done as a pratial fulfillment of the requirements of UOM's EN3030 Circuits and Systems Design module.

The primary objective of this project was to design a Microprocessor and a CPU (Central Processing Unit) which can downsample a given 256x256 greyscale 8-bit image and generate correct results. The coding was done using Verilog Hardware Description Language (HDL). Xilinx Vivado was used as the analysis and synthesis tool for the design of the processor and for the simulation of Verilog HDL designs.

Input Image Output Image

Getting Started

Run the simulation with the pre configured settings (default image)

  1. Processor directory includes the latest working version of the processor which was tested and run successfully in Xilinx Vivado 2018.2. The design is therefore not tested on any of the previos versions of the software.
  2. To simulate the processor, open Vivado software. Then use its Open Project wizard to open the Processor.xpr file locatd in the Processor directory.
  3. Once the project is loaded, run the simulation. If the simulation is successful you will see a waveform similar to that of the below figure with the complete1. signal HIGH.
  1. Once the simulation is complete, it will generate a text file named output.txt in the DownSampleMe directory. It contains the 1D binary representation of the resultatnt down sampled image of the original image that we have input to the simulation.
  2. To visualize the output image, open this (Google Colab Notebook), upload the output.txt file to colab's file system and run the cell depicted in the below figure.

Change the input image

  1. Open this (Google Colab Notebook) , upload a 256x256 image file to colab's file system and run the cell depicted in the below figure. This will load the required image to the notebook.
  1. Then run the next immediate cell, to generate the verilog compatible format of the image. This will create a new text file named <your_image_name>.txt as shown in the figure given below.
  1. Copy everything in that <your_image_name>.txt file by pressing Ctrl + A and replace the following code lines (starting from ram[20] to ram[65555]) in the Ram.v file. This file can be opened using the vivado 's bult-in editor. Once the lines are replaced, save the file and run the simulation again.
ram[20] = 8'b10100101;
ram[21] = 8'b10100001;
ram[22] = 8'b10011101;
ram[23] = 8'b10011101;
ram[24] = 8'b10100001;
          :
          :
          :
ram[65550] = 8'b01000101;
ram[65551] = 8'b01010010;
ram[65552] = 8'b01011101;
ram[65553] = 8'b01100110;
ram[65554] = 8'b01101100;
ram[65555] = 8'b01101110;
  1. Follow the same steps mentioned previously to visualize the new output.

Resources

  • Documentation: Google Doc, offline available in the directory Report/FPGA report .pdf

  • Assembly Code of the downsampling algorithm: Google Doc, offline available in the directory Micro Instructions/Assembly Code of the Algorithm.pdf

  • Look Up Table for the Control Unit: Google Sheet, offline available in the directory Control LUT/Control Unit LUT - Sheet1.pdf

  • Python Scripts: Google Colab Notebook, offline available in the directory Image Generation/EN3030_Processor_Design.ipynb

Contributors