MIO

FPGA Firmware

A Xilinx project file (.xise) is available here.

Pin Assignments

• RJ45 Jack / TLU Port
  Connect the EUDET TLU here.

• LEMO Connectors
  Note: all inputs and outputs are using 3.3V CMOS logic levels
  RX0: External Trigger Input (also Trigger Input for TDC)
  RX1: Trigger Veto Input
  RX2: TDC Input
  TX0: Command (to FE) Busy
  TX1: Trigger Busy
  TX2: Loop-through TLU Trigger (from TLU Port)

• Pin Header P9
  Not used.

Status LEDs

LED 5 (System and SRAM FIFO status):

• flashing at 1Hz: OK
• flashing at 3Hz: TLU connected to RJ45 jack (auto sensing)
• off: DCM not locked
• on: SRAM FIFO full

LED 1-4 (RX FIFO status):

• flashing at 1Hz: OK
• flashing at 3Hz: RX decoder error counter >0
• off: no RX sync
• on: RX FIFO overflow || RX FIFO full