Files

CommitHistoryVisualizer
Lab1
Lab2
- ADDER_8bit.v
- DECODER.v
- FADDER.v
- Lab_Sheet_2_Final.pdf
- README.md
- adder_32bit.v
- comparator_4bit.v
- decoder_3to1.v
- fadder_bhvrl.v
- fadder_dec.v
- mux16to1_glvl.v
- mux4to1_gate.v
- mux4to1_glvl.v
- tb_comparator_4bit.v
- tb_fadder_dec.v
- tb_mux16to1_glvl.v
- tb_mux4to1_glvl
- tb_mux4to1_glvl.v
- test
- test.v
- testbench_adder_32bit.v
- testbench_adder_8bit.v
- testbench_fadder.v
Lab3
Lab4
Lab5
Lab6
Lab7
Lab8
LabTestPractice
PracticeQuestions
.gitignore
README.md
Samir Palnitkar - Verilog HDL-Prentice Hall (1996).pdf
Verilog_Notes.pdf
_config.yml

README.md

Lab1 exercises completed, README details added

Aug 26, 2020

046f492 · Aug 26, 2020

Lab Sheet 2

LearningObjectives

Combinational digital circuit modeling
Constructing a larger module using a smaller module