Files

CommitHistoryVisualizer
Lab1
Lab2
Lab3
Lab4
- Lab4_sheet_aludesign.pdf
- MainCU.PNG
- README.md
- alu.v
- aluCU.v
- fulladder_32bit.v
- mainCU.v
- module_32bitAND.v
- module_32bitOR.v
- mux_2to1.v
- mux_2to1_32bit.v
- mux_2to1_8bit.v
- mux_3to1_32bit.v
- tbALU.v
- tb_aluCU.PNG
- tb_aluCU.v
- test_32bitAND.v
- test_32bitOR.v
- test_32bitadder.v
- test_mainCU.v
- test_mux_2to1_32bit.v
- test_mux_2to1_8bit.PNG
- test_mux_2to1_8bit.v
- test_mux_3to1_32bit.v
Lab5
Lab6
Lab7
Lab8
LabTestPractice
PracticeQuestions
.gitignore
README.md
Samir Palnitkar - Verilog HDL-Prentice Hall (1996).pdf
Verilog_Notes.pdf
_config.yml

README.md

Lab1 exercises completed, README details added

Aug 26, 2020

046f492 · Aug 26, 2020

Lab Sheet 4

LearningObjectives

To design a Simple MIPS ALU in a step by step manner
To design the main Control PLA to generate control signals
To design the ALU control Logic