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core-v-mini-mcu.core
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CAPI=2:
# Copyright 2022 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
name: openhwgroup.org:systems:core-v-mini-mcu
description: CORE-V MINI-MCU Top.
filesets:
files_rtl_generic:
depend:
- x-heep::packages
- openhwgroup.org:ip:cv32e40p
- openhwgroup.org:ip:cv32e40x
- openhwgroup.org:ip:cve2
- pulp-platform.org:ip:gpio
- pulp-platform.org::common_cells
- pulp-platform.org::cluster_interconnect
- pulp-platform.org::riscv_dbg
- pulp-platform.org::register_interface
- openhwgroup.org:ip:soc_ctrl
- lowrisc:ip:uart:0.1
- lowrisc:ip:rv_plic_example:0.1
- lowrisc:ip:rv_timer:0.1
- lowrisc:ip:spi_host:1.0
- lowrisc:ip:i2c:0.1
- yosyshq:picorv32_spimemio:0-r1
- x-heep:obi_spimemio:0.1.0
- x-heep:ip:boot_rom
- x-heep:ip:dma
- x-heep:ip:power_manager
- x-heep:ip:fast_intr_ctrl
- x-heep:ip:pdm2pcm
files:
- hw/core-v-mini-mcu/core_v_mini_mcu.sv
- hw/core-v-mini-mcu/cpu_subsystem.sv
- hw/core-v-mini-mcu/memory_subsystem.sv
- hw/core-v-mini-mcu/system_bus.sv
- hw/core-v-mini-mcu/system_xbar.sv
- hw/core-v-mini-mcu/spi_subsystem.sv
- hw/core-v-mini-mcu/debug_subsystem.sv
- hw/core-v-mini-mcu/peripheral_subsystem.sv
- hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
file_type: systemVerilogSource
rtl-simulation:
depend:
- pulp-platform.org::tech_cells_generic
files:
- hw/simulation/sram_wrapper.sv
- hw/simulation/pad_cell_bypass_input.sv
- hw/simulation/pad_cell_bypass_output.sv
- hw/simulation/pad_cell_inout.sv
- hw/simulation/pad_cell_input.sv
- hw/simulation/pad_cell_output.sv
file_type: systemVerilogSource
x_heep_system:
depend:
- x-heep::packages
- x-heep:ip:pad_control
files:
- hw/system/x_heep_system.sv
- hw/system/pad_ring.sv
file_type: systemVerilogSource
tb-utils:
depend:
- x-heep::tb-utils
files_verilator_waiver:
depend:
- openhwgroup.org:ip:verilator_waiver
files:
- hw/core-v-mini-mcu/core_v_mini_mcu.vlt
- hw/ip/soc_ctrl/soc_ctrl.vlt
- hw/ip/boot_rom/boot_rom.vlt
- hw/ip/obi_spimemio/obi_spimemio.vlt
- hw/ip/dma/dma.vlt
- hw/ip/pdm2pcm/pdm2pcm.vlt
- hw/ip_examples/pdm2pcm_dummy/pdm2pcm_dummy.vlt
- hw/ip/power_manager/power_manager.vlt
- hw/ip/fast_intr_ctrl/fast_intr_ctrl.vlt
- hw/system/pad_control/pad_control.vlt
- hw/system/x_heep_system.vlt
- hw/simulation/simulation.vlt
file_type: vlt
rtl-fpga:
files:
- hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
- hw/fpga/sram_wrapper.sv
file_type: systemVerilogSource
ip-fpga:
files:
- hw/fpga/scripts/xilinx_generate_clk_wizard.tcl: { file_type: tclSource }
- hw/fpga/scripts/generate_sram.tcl: { file_type: tclSource }
- hw/fpga/prim_xilinx_clk.sv: { file_type: systemVerilogSource }
- hw/fpga/cv32e40p_xilinx_clock_gate.sv: { file_type: systemVerilogSource }
- hw/fpga/cv32e40x_xilinx_clock_gate.sv: { file_type: systemVerilogSource }
- hw/fpga/cve2_xilinx_clock_gate.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_input_xilinx.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_output_xilinx.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_inout_xilinx.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_bypass_input_xilinx.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_bypass_output_xilinx.sv: { file_type: systemVerilogSource }
fpga-arm-emulation:
depend:
- pulp-platform.org::axi_spi_slave
files:
- linux_femu/scripts/xilinx_generate_processing_system.tcl: {file_type: tclSource}
- linux_femu/rtl/axi_address_hijacker.v: {file_type: verilogSource}
- linux_femu/rtl/linux_femu.sv: {file_type: systemVerilogSource}
- linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
- linux_femu/constraints/constraints.xdc: {file_type: xdc}
ip-asic:
depend:
- technology::prim_mytech
rtl-sky130:
files:
- hw/asic/sky130/sram_wrapper.sv
- hw/vendor/openhwgroup_cv32e20/bhv/cve2_sim_clock_gate.sv #as for now use the simulation clk gating
- hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_sim_clock_gate.sv
- hw/vendor/pulp_platform_tech_cells_generic/src/deprecated/pulp_clk_cells.sv #as for now use the simulation clk cells
- hw/vendor/pulp_platform_tech_cells_generic/src/deprecated/cluster_clk_cells.sv #as for now use the simulation clk cells
- hw/vendor/pulp_platform_tech_cells_generic/src/rtl/tc_clk.sv #as for now use the simulation clk cells
file_type: systemVerilogSource
lib-sky130:
files:
- hw/asic/sky130/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib : { copyto: lib/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib }
xdc-fpga-nexys:
files:
- hw/fpga/constraints/nexys/pin_assign.xdc
- hw/fpga/constraints/nexys/constraints.xdc
file_type: xdc
xdc-fpga-pynq-z2:
files:
- hw/fpga/constraints/pynq-z2/pin_assign.xdc
- hw/fpga/constraints/pynq-z2/constraints.xdc
file_type: xdc
netlist-fpga:
files:
- build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
file_type: verilogSource
# Scripts for hooks
post_build_modelsim_scripts:
files:
- scripts/sim/modelsim/post_build_modelsim_vopt.sh
file_type: user
pre_build_remote_bitbang:
files:
- scripts/sim/compile_remote_bitbang.sh
file_type: user
pre_build_uartdpi:
files:
- scripts/sim/compile_uart_dpi.sh
file_type: user
cfile_uartdpi:
files:
- ./hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.c
- ./hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.h: { is_include_file: true }
file_type: cSource
pre_patch_modelsim_Makefile:
files:
- scripts/sim/modelsim/patch_modelsim_Makefile.py
file_type: user
pre_patch_vcs_ams_Makefile:
files:
- scripts/sim/vcs/patch_vcs_ams_Makefile.py
file_type: user
tb-verilator:
files:
- tb/tb_top.cpp
file_type: cppSource
tb-sv:
files:
- tb/tb_top.sv
file_type: systemVerilogSource
openroad_base_files:
files:
- flow/OpenROAD-flow-scripts/flow/Makefile : {file_type: Makefile}
depend:
- core-v-mini:util:sv2v
openroad_sky130_files:
files:
- flow/sky130/config.mk : {file_type: configFile}
- flow/sky130/constraint.sdc : {file_type: SDC}
parameters:
COREV_PULP:
datatype: int
paramtype: vlogparam
default: 0
FPU:
datatype: int
paramtype: vlogparam
default: 0
JTAG_DPI:
datatype: int
paramtype: vlogparam
default: 0
USE_EXTERNAL_DEVICE_EXAMPLE:
datatype: bool
paramtype: vlogdefine
default: false
USE_UPF:
datatype: bool
paramtype: vlogdefine
default: false
SYNTHESIS:
datatype: bool
paramtype: vlogdefine
default: false
VERILATOR: #used by SV2V
datatype: bool
paramtype: vlogdefine
default: false
FPGA_NETLIST:
datatype: bool
paramtype: vlogdefine
default: false
# Make the parameter known to FuseSoC to enable overrides from the
# command line. If not overwritten, use the generic technology library.
PRIM_DEFAULT_IMPL:
datatype: str
paramtype: vlogdefine
description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
default: prim_pkg::ImplGeneri
scripts:
post_build_modelsim_scripts:
cmd:
- sh
- ../../../scripts/sim/modelsim/post_build_modelsim_vopt.sh
pre_build_remote_bitbang:
cmd:
- sh
- ../../../scripts/sim/compile_remote_bitbang.sh
pre_build_uartdpi:
cmd:
- sh
- ../../../scripts/sim/compile_uart_dpi.sh
pre_patch_modelsim_Makefile:
cmd:
- python
- ../../../scripts/sim/modelsim/patch_modelsim_Makefile.py
pre_patch_vcs_ams_Makefile:
cmd:
- python
- ../../../scripts/sim/vcs/patch_vcs_ams_Makefile.py
targets:
default: &default_target
filesets:
- files_rtl_generic
- target_sim ? (rtl-simulation)
- target_sim ? (tool_verilator? (files_verilator_waiver))
toplevel: [core_v_mini_mcu]
sim:
<<: *default_target
default_tool: modelsim
filesets_append:
- tb-utils
- tool_modelsim? (pre_build_remote_bitbang)
- tool_modelsim? (pre_build_uartdpi)
- tool_modelsim? (pre_patch_modelsim_Makefile)
- tool_vcs? (cfile_uartdpi)
- tool_vcs? (pre_build_remote_bitbang)
- tool_verilator? (tb-verilator)
- tool_modelsim? (tb-sv)
- tool_vcs? (tb-sv)
- "!integrated_heep? (x_heep_system)"
toplevel:
- tool_modelsim? (tb_top)
- tool_vcs? (tb_top)
- tool_verilator? (testharness)
hooks:
pre_build:
- tool_modelsim? (pre_build_uartdpi)
- tool_modelsim? (pre_build_remote_bitbang)
- tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
- ams_sim? (pre_patch_vcs_ams_Makefile)
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- use_jtag_dpi? (JTAG_DPI=1)
- "!use_jtag_dpi? (JTAG_DPI=0)"
- use_external_device_example? (USE_EXTERNAL_DEVICE_EXAMPLE=true)
- use_upf? (USE_UPF=true)
tools:
modelsim:
vlog_options:
- -override_timescale 1ns/1ps
- -suppress vlog-2583
- -suppress vlog-2577
- -pedanticerrors
- -define MODELSIM
vsim_options:
- -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
- -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
vcs:
vcs_options:
- -override_timescale=1ns/1ps
- -assert disable_cover
- -assert svaext
- -debug_access+all+dmptf
- -fgp
- -full64
- -kdb
- -notice
- -ntb_opts error
- -race=all
- -xlrm uniq_prior_final
- -CFLAGS "-std=c++14 -pthread"
- -LDFLAGS "-pthread -lutil"
- +lint=TFIPC-L
- -V
verilator:
mode: cc
verilator_options:
- '--cc'
- '--trace'
- '--trace-fst'
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '--x-assign unique'
- '--x-initial unique'
- '--exe tb_top.cpp'
- '-CFLAGS "-std=c++11 -Wall -g -fpermissive"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
nexys-a7-100t:
<<: *default_target
default_tool: vivado
description: Digilent Nexys-A7-100T Board
filesets_append:
- rtl-fpga
- ip-fpga
- xdc-fpga-nexys
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- SYNTHESIS=true
tools:
vivado:
part: xc7a100tcsg324-1
toplevel: [xilinx_core_v_mini_mcu_wrapper]
pynq-z2:
<<: *default_target
default_tool: vivado
description: TUL Pynq-Z2 Board
filesets_append:
- x_heep_system
- rtl-fpga
- ip-fpga
- xdc-fpga-pynq-z2
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- SYNTHESIS=true
tools:
vivado:
part: xc7z020clg400-1
toplevel: [xilinx_core_v_mini_mcu_wrapper]
pynq-z2-arm-emulation:
<<: *default_target
default_tool: vivado
description: TUL Pynq-Z2 Board
filesets_append:
- x_heep_system
- rtl-fpga
- ip-fpga
- fpga-arm-emulation
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- SYNTHESIS=true
tools:
vivado:
part: xc7z020clg400-1
jobs: 4
toplevel: [linux_femu]
sim_nexys_netlist:
filesets:
- netlist-fpga
- tb-rtl
- post_build_modelsim_scripts
toplevel: [tb_top_vopt]
hooks:
post_build: [post_build_modelsim_scripts]
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- FPGA_NETLIST=true
tools:
modelsim:
vlog_options:
- -override_timescale 1ns/1ps
- -suppress vlog-2583
- -suppress vlog-2577
- -pedanticerrors
asic_synthesis:
<<: *default_target
default_tool: design_compiler
description: Design Compiler Script
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- SYNTHESIS=true
filesets_append:
- ip-asic
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::your_target_technology
toplevel: [core_v_mini_mcu]
tools:
design_compiler:
script_dir:
- ../../../scripts/synthesis/dc_shell
report_dir:
- report
dc_script:
- dc_script.tcl
asic_yosys_synthesis:
<<: *default_target
default_tool: openroad
description: yosys
parameters:
- use_cv32e40p_corev_pulp? (COREV_PULP=1)
- "!use_cv32e40p_corev_pulp? (COREV_PULP=0)"
- use_cv32e40p_fpu? (FPU=1)
- "!use_cv32e40p_fpu? (FPU=0)"
- SYNTHESIS=true
- VERILATOR=true
filesets_append:
- use_sky130? (rtl-sky130)
- lib-sky130
- openroad_base_files
- openroad_sky130_files
toplevel: [core_v_mini_mcu]
tools:
openroad:
flow_path: flow/OpenROAD-flow-scripts/flow
make_target: synth