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dev, sim: Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01 #355
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the verilator testbench of VexRiscv alone doesn't implement JTAG, but some more direct connections. You can ignore all the JTAG related error it throws at you ^^ |
My origin problem is that I was hoping I could replicate the problem in simulation. How should I try to debug this regression in simulation? |
Ahhh, then you can use the MuraxSim (SpinalSim), See : This virtualize a proper jtag. Hardware issue should be reproducable there aswell. What kind of regression exactly do you get on your hardware ? |
Currently I am developing against a local SpinalHDL
dev
branch, along with local VexRiscvdev
and the VexRiscv-specific latest OpenOCD (i.e. using the "old" VexRiscv debug module") and I am seeing a possible regression during working with OpenOCD on my hardware. I am investigating. So I went back to VexRiscv/Sim/OpenOCD as per the README.In simulation, I get different errors starting OpenOCD, but things do seem to work. But I do see errors I never saw before, are the following errors innocent?
This is the set of sources (current tips of
dev
,dev
, riscv-spinal` branches, in this order) for:I am following the
README.md
:The text was updated successfully, but these errors were encountered: