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dhd_msgbuf.c
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dhd_msgbuf.c
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/**
* @file definition of host message ring functionality
* Provides type definitions and function prototypes used to link the
* DHD OS, bus, and protocol modules.
*
* Copyright (C) 2022, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Open:>>
*
* $Id$
*/
/** XXX Twiki: [PCIeFullDongleArchitecture] */
#include <typedefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <bcmmsgbuf.h>
#include <bcmendian.h>
#include <bcmstdlib_s.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhd_proto.h>
#include <dhd_bus.h>
#include <dhd_dbg.h>
#include <siutils.h>
#include <dhd_debug.h>
#ifdef EXT_STA
#include <wlc_cfg.h>
#include <wlc_pub.h>
#include <wl_port_if.h>
#endif /* EXT_STA */
#include <dhd_flowring.h>
#include <pcie_core.h>
#include <bcmpcie.h>
#include <dhd_pcie.h>
#include <dhd_config.h>
#if defined(DHD_LB)
#if !defined(LINUX) && !defined(linux) && !defined(OEM_ANDROID)
#error "DHD Loadbalancing only supported on LINUX | OEM_ANDROID"
#endif /* !LINUX && !OEM_ANDROID */
#include <linux/cpu.h>
#include <bcm_ring.h>
#define DHD_LB_WORKQ_SZ (8192)
#define DHD_LB_WORKQ_SYNC (16)
#define DHD_LB_WORK_SCHED (DHD_LB_WORKQ_SYNC * 2)
#endif /* DHD_LB */
#include <etd.h>
#include <hnd_debug.h>
#include <bcmtlv.h>
#include <hnd_armtrap.h>
#include <dnglevent.h>
#ifdef DHD_PKT_LOGGING
#include <dhd_pktlog.h>
#include <dhd_linux_pktdump.h>
#endif /* DHD_PKT_LOGGING */
#ifdef DHD_EWPR_VER2
#include <dhd_bitpack.h>
#endif /* DHD_EWPR_VER2 */
extern char dhd_version[];
extern char fw_version[];
/**
* Host configures a soft doorbell for d2h rings, by specifying a 32bit host
* address where a value must be written. Host may also interrupt coalescing
* on this soft doorbell.
* Use Case: Hosts with network processors, may register with the dongle the
* network processor's thread wakeup register and a value corresponding to the
* core/thread context. Dongle will issue a write transaction <address,value>
* to the PCIE RC which will need to be routed to the mapped register space, by
* the host.
*/
/* #define DHD_D2H_SOFT_DOORBELL_SUPPORT */
/* Dependency Check */
#if defined(IOCTLRESP_USE_CONSTMEM) && defined(DHD_USE_STATIC_CTRLBUF)
#error "DHD_USE_STATIC_CTRLBUF is NOT working with DHD_USE_OSLPKT_FOR_RESPBUF"
#endif /* IOCTLRESP_USE_CONSTMEM && DHD_USE_STATIC_CTRLBUF */
#define RETRIES 2 /* # of retries to retrieve matching ioctl response */
/* For legacy firmware where pcie shared structure does not have max_host_rxbufs, use this */
#define LEGACY_MAX_RXBUFPOST 256u
/* Read index update Magic sequence */
#define DHD_DMA_INDX_SEQ_H2D_DB_MAGIC 0xDDDDDDDDAu
#define DHD_RDPTR_UPDATE_H2D_DB_MAGIC(ring) (0xDD000000 | (ring->idx << 16u) | ring->rd)
/* Write index update Magic sequence */
#define DHD_WRPTR_UPDATE_H2D_DB_MAGIC(ring) (0xFF000000 | (ring->idx << 16u) | ring->wr)
#define DHD_AGGR_H2D_DB_MAGIC 0xFFFFFFFAu
#define DHD_STOP_QUEUE_THRESHOLD 200
#define DHD_START_QUEUE_THRESHOLD 100
#define RX_DMA_OFFSET 8 /* Mem2mem DMA inserts an extra 8 */
#define IOCT_RETBUF_SIZE (RX_DMA_OFFSET + WLC_IOCTL_MAXLEN)
/* flags for ioctl pending status */
#define MSGBUF_IOCTL_ACK_PENDING (1<<0)
#define MSGBUF_IOCTL_RESP_PENDING (1<<1)
#define DHD_IOCTL_REQ_PKTBUFSZ 2048
#define MSGBUF_IOCTL_MAX_RQSTLEN (DHD_IOCTL_REQ_PKTBUFSZ - H2DRING_CTRL_SUB_ITEMSIZE)
/**
* XXX: DMA_ALIGN_LEN use is overloaded:
* - as align bits: in DMA_ALLOC_CONSISTENT 1 << 4
* - in ensuring that a buffer's va is 4 Byte aligned
* - in rounding up a buffer length to 4 Bytes.
*/
#define DMA_ALIGN_LEN 4
#define DMA_D2H_SCRATCH_BUF_LEN 8
#define DMA_XFER_LEN_LIMIT 0x400000
#ifdef BCM_HOST_BUF
#ifndef DMA_HOST_BUFFER_LEN
#define DMA_HOST_BUFFER_LEN 0x200000
#endif
#endif /* BCM_HOST_BUF */
#define DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ 8192
#define DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D 1
#define DHD_FLOWRING_MAX_EVENTBUF_POST 32
#define DHD_FLOWRING_MAX_IOCTLRESPBUF_POST 8
#define DHD_H2D_INFORING_MAX_BUF_POST 32
#define DHD_MAX_TSBUF_POST 8
#define DHD_PROT_FUNCS 43
/* Length of buffer in host for bus throughput measurement */
#define DHD_BUS_TPUT_BUF_LEN 2048
#define TXP_FLUSH_NITEMS
/* optimization to write "n" tx items at a time to ring */
#define TXP_FLUSH_MAX_ITEMS_FLUSH_CNT 48
#define RING_NAME_MAX_LENGTH 24
#define CTRLSUB_HOSTTS_MEESAGE_SIZE 1024
/* Giving room before ioctl_trans_id rollsover. */
#define BUFFER_BEFORE_ROLLOVER 300
/* 512K memory + 32K registers */
#define SNAPSHOT_UPLOAD_BUF_SIZE ((512 + 32) * 1024)
struct msgbuf_ring; /* ring context for common and flow rings */
#ifdef DHD_HMAPTEST
/* 5 * DMA_CONSISTENT_ALIGN as different tests use upto 4th page */
#define HMAP_SANDBOX_BUFFER_LEN (DMA_CONSISTENT_ALIGN * 5) /* for a 4k page this is 20K */
/**
* for D11 DMA HMAPTEST thes states are as follows
* iovar sets ACTIVE state
* next TXPOST / RXPOST sets POSTED state
* on TXCPL / RXCPL POSTED + pktid match does buffer free nd state changed to INACTIVE
* This ensures that on an iovar only one buffer is replaced from sandbox area
*/
#define HMAPTEST_D11_TX_INACTIVE 0
#define HMAPTEST_D11_TX_ACTIVE 1
#define HMAPTEST_D11_TX_POSTED 2
#define HMAPTEST_D11_RX_INACTIVE 0
#define HMAPTEST_D11_RX_ACTIVE 1
#define HMAPTEST_D11_RX_POSTED 2
#endif /* DHD_HMAPTEST */
#define PCIE_DMA_LOOPBACK 0
#define D11_DMA_LOOPBACK 1
#define BMC_DMA_LOOPBACK 2
/**
* PCIE D2H DMA Complete Sync Modes
*
* Firmware may interrupt the host, prior to the D2H Mem2Mem DMA completes into
* Host system memory. A WAR using one of 3 approaches is needed:
* 1. Dongle places a modulo-253 seqnum in last word of each D2H message
* 2. XOR Checksum, with epoch# in each work item. Dongle builds an XOR checksum
* writes in the last word of each work item. Each work item has a seqnum
* number = sequence num % 253.
*
* 3. Read Barrier: Dongle does a host memory read access prior to posting an
* interrupt, ensuring that D2H data transfer indeed completed.
* 4. Dongle DMA's all indices after producing items in the D2H ring, flushing
* ring contents before the indices.
*
* Host does not sync for DMA to complete with option #3 or #4, and a noop sync
* callback (see dhd_prot_d2h_sync_none) may be bound.
*
* Dongle advertizes host side sync mechanism requirements.
*/
#ifdef PCIE_D2H_SYNC_RETRY_CNT_ONE
#define PCIE_D2H_SYNC_WAIT_TRIES (1U)
#define PCIE_D2H_SYNC_NUM_OF_STEPS (1U)
#define PCIE_D2H_SYNC_DELAY (1UL) /* in terms of usecs */
#else
#define PCIE_D2H_SYNC_WAIT_TRIES (512U)
#define PCIE_D2H_SYNC_NUM_OF_STEPS (5U)
#define PCIE_D2H_SYNC_DELAY (100UL) /* in terms of usecs */
#endif /* PCIE_D2H_SYNC_RETRY_CNT_ONE */
/**
* Custom callback attached based upon D2H DMA Sync mode advertized by dongle.
*
* On success: return cmn_msg_hdr_t::msg_type
* On failure: return 0 (invalid msg_type)
*/
typedef uint8 (* d2h_sync_cb_t)(dhd_pub_t *dhd, struct msgbuf_ring *ring,
volatile cmn_msg_hdr_t *msg, int msglen);
void dhd_prot_debug_ring_info(dhd_pub_t *dhd);
/**
* Custom callback attached based upon D2H DMA Sync mode advertized by dongle.
* For EDL messages.
*
* On success: return cmn_msg_hdr_t::msg_type
* On failure: return 0 (invalid msg_type)
*/
#ifdef EWP_EDL
typedef int (* d2h_edl_sync_cb_t)(dhd_pub_t *dhd, struct msgbuf_ring *ring,
volatile cmn_msg_hdr_t *msg);
#endif /* EWP_EDL */
/*
* +----------------------------------------------------------------------------
*
* RingIds and FlowId are not equivalent as ringids include D2H rings whereas
* flowids do not.
*
* Dongle advertizes the max H2D rings, as max_sub_queues = 'N' which includes
* the H2D common rings as well as the (N-BCMPCIE_H2D_COMMON_MSGRINGS) flowrings
*
* Here is a sample mapping for (based on PCIE Full Dongle Rev5) where,
* BCMPCIE_H2D_COMMON_MSGRINGS = 2, i.e. 2 H2D common rings,
* BCMPCIE_COMMON_MSGRINGS = 5, i.e. include 3 D2H common rings.
*
* H2D Control Submit RingId = 0 FlowId = 0 reserved never allocated
* H2D RxPost Submit RingId = 1 FlowId = 1 reserved never allocated
*
* D2H Control Complete RingId = 2
* D2H Transmit Complete RingId = 3
* D2H Receive Complete RingId = 4
*
* H2D TxPost FLOWRING RingId = 5 FlowId = 2 (1st flowring)
* H2D TxPost FLOWRING RingId = 6 FlowId = 3 (2nd flowring)
* H2D TxPost FLOWRING RingId = 5 + (N-1) FlowId = (N-1) (Nth flowring)
*
* When TxPost FlowId(s) are allocated, the FlowIds [0..FLOWID_RESERVED) are
* unused, where FLOWID_RESERVED is BCMPCIE_H2D_COMMON_MSGRINGS.
*
* Example: when a system supports 4 bc/mc and 128 uc flowrings, with
* BCMPCIE_H2D_COMMON_MSGRINGS = 2, and BCMPCIE_H2D_COMMON_MSGRINGS = 5, and the
* FlowId values would be in the range [2..133] and the corresponding
* RingId values would be in the range [5..136].
*
* The flowId allocator, may chose to, allocate Flowids:
* bc/mc (per virtual interface) in one consecutive range [2..(2+VIFS))
* X# of uc flowids in consecutive ranges (per station Id), where X is the
* packet's access category (e.g. 4 uc flowids per station).
*
* CAUTION:
* When DMA indices array feature is used, RingId=5, corresponding to the 0th
* FLOWRING, will actually use the FlowId as index into the H2D DMA index,
* since the FlowId truly represents the index in the H2D DMA indices array.
*
* Likewise, in the D2H direction, the RingId - BCMPCIE_H2D_COMMON_MSGRINGS,
* will represent the index in the D2H DMA indices array.
*
* +----------------------------------------------------------------------------
*/
/* First TxPost Flowring Id */
#define DHD_FLOWRING_START_FLOWID BCMPCIE_H2D_COMMON_MSGRINGS
/* Determine whether a ringid belongs to a TxPost flowring */
#define DHD_IS_FLOWRING(ringid, max_flow_rings) \
((ringid) >= BCMPCIE_COMMON_MSGRINGS && \
(ringid) < ((max_flow_rings) + BCMPCIE_COMMON_MSGRINGS))
/* Convert a H2D TxPost FlowId to a MsgBuf RingId */
#define DHD_FLOWID_TO_RINGID(flowid) \
(BCMPCIE_COMMON_MSGRINGS + ((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS))
/* Convert a MsgBuf RingId to a H2D TxPost FlowId */
#define DHD_RINGID_TO_FLOWID(ringid) \
(BCMPCIE_H2D_COMMON_MSGRINGS + ((ringid) - BCMPCIE_COMMON_MSGRINGS))
/* Convert a H2D MsgBuf RingId to an offset index into the H2D DMA indices array
* This may be used for the H2D DMA WR index array or H2D DMA RD index array or
* any array of H2D rings.
*/
#define DHD_H2D_RING_OFFSET(ringid) \
(((ringid) >= BCMPCIE_COMMON_MSGRINGS) ? DHD_RINGID_TO_FLOWID(ringid) : (ringid))
/* Convert a H2D MsgBuf Flowring Id to an offset index into the H2D DMA indices array
* This may be used for IFRM.
*/
#define DHD_H2D_FRM_FLOW_RING_OFFSET(ringid) \
((ringid) - BCMPCIE_COMMON_MSGRINGS)
/* Convert a D2H MsgBuf RingId to an offset index into the D2H DMA indices array
* This may be used for the D2H DMA WR index array or D2H DMA RD index array or
* any array of D2H rings.
* d2h debug ring is located at the end, i.e. after all the tx flow rings and h2d debug ring
* max_h2d_rings: total number of h2d rings
*/
#define DHD_D2H_RING_OFFSET(ringid, max_h2d_rings) \
((ringid) > (max_h2d_rings) ? \
((ringid) - max_h2d_rings) : \
((ringid) - BCMPCIE_H2D_COMMON_MSGRINGS))
/* Convert a D2H DMA Indices Offset to a RingId */
#define DHD_D2H_RINGID(offset) \
((offset) + BCMPCIE_H2D_COMMON_MSGRINGS)
/* XXX: The ringid and flowid and dma indices array index idiosyncracy is error
* prone. While a simplification is possible, the backward compatability
* requirement (DHD should operate with any PCIE rev version of firmware),
* limits what may be accomplished.
*
* At the minimum, implementation should use macros for any conversions
* facilitating introduction of future PCIE FD revs that need more "common" or
* other dynamic rings.
*/
/* XXX: Presently there is no need for maintaining both a dmah and a secdmah */
#define DHD_DMAH_NULL ((void*)NULL)
/*
* Pad a DMA-able buffer by an additional cachline. If the end of the DMA-able
* buffer does not occupy the entire cacheline, and another object is placed
* following the DMA-able buffer, data corruption may occur if the DMA-able
* buffer is used to DMAing into (e.g. D2H direction), when HW cache coherency
* is not available.
*/
#if defined(L1_CACHE_BYTES)
#define DHD_DMA_PAD (L1_CACHE_BYTES)
#else
#define DHD_DMA_PAD (128)
#endif
/*
* +----------------------------------------------------------------------------
* Flowring Pool
*
* Unlike common rings, which are attached very early on (dhd_prot_attach),
* flowrings are dynamically instantiated. Moreover, flowrings may require a
* larger DMA-able buffer. To avoid issues with fragmented cache coherent
* DMA-able memory, a pre-allocated pool of msgbuf_ring_t is allocated once.
* The DMA-able buffers are attached to these pre-allocated msgbuf_ring.
*
* Each DMA-able buffer may be allocated independently, or may be carved out
* of a single large contiguous region that is registered with the protocol
* layer into flowrings_dma_buf. On a 64bit platform, this contiguous region
* may not span 0x00000000FFFFFFFF (avoid dongle side 64bit ptr arithmetic).
*
* No flowring pool action is performed in dhd_prot_attach(), as the number
* of h2d rings is not yet known.
*
* In dhd_prot_init(), the dongle advertized number of h2d rings is used to
* determine the number of flowrings required, and a pool of msgbuf_rings are
* allocated and a DMA-able buffer (carved or allocated) is attached.
* See: dhd_prot_flowrings_pool_attach()
*
* A flowring msgbuf_ring object may be fetched from this pool during flowring
* creation, using the flowid. Likewise, flowrings may be freed back into the
* pool on flowring deletion.
* See: dhd_prot_flowrings_pool_fetch(), dhd_prot_flowrings_pool_release()
*
* In dhd_prot_detach(), the flowring pool is detached. The DMA-able buffers
* are detached (returned back to the carved region or freed), and the pool of
* msgbuf_ring and any objects allocated against it are freed.
* See: dhd_prot_flowrings_pool_detach()
*
* In dhd_prot_reset(), the flowring pool is simply reset by returning it to a
* state as-if upon an attach. All DMA-able buffers are retained.
* Following a dhd_prot_reset(), in a subsequent dhd_prot_init(), the flowring
* pool attach will notice that the pool persists and continue to use it. This
* will avoid the case of a fragmented DMA-able region.
*
* +----------------------------------------------------------------------------
*/
/* Conversion of a flowid to a flowring pool index */
#define DHD_FLOWRINGS_POOL_OFFSET(flowid) \
((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS)
/* Fetch the msgbuf_ring_t from the flowring pool given a flowid */
#define DHD_RING_IN_FLOWRINGS_POOL(prot, flowid) \
(msgbuf_ring_t*)((prot)->h2d_flowrings_pool) + \
DHD_FLOWRINGS_POOL_OFFSET(flowid)
/* Traverse each flowring in the flowring pool, assigning ring and flowid */
#define FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid, total_flowrings) \
for ((flowid) = DHD_FLOWRING_START_FLOWID, \
(ring) = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid); \
(flowid) < ((total_flowrings) + DHD_FLOWRING_START_FLOWID); \
(ring)++, (flowid)++)
/* Used in loopback tests */
typedef struct dhd_dmaxfer {
dhd_dma_buf_t srcmem;
dhd_dma_buf_t dstmem;
uint32 srcdelay;
uint32 destdelay;
uint32 len;
bool in_progress;
uint64 start_usec;
uint64 time_taken;
uint32 d11_lpbk;
int status;
} dhd_dmaxfer_t;
#ifdef DHD_HMAPTEST
/* Used in HMAP test */
typedef struct dhd_hmaptest {
dhd_dma_buf_t mem;
uint32 len;
bool in_progress;
uint32 is_write;
uint32 accesstype;
uint64 start_usec;
uint32 offset;
} dhd_hmaptest_t;
#endif /* DHD_HMAPTEST */
/**
* msgbuf_ring : This object manages the host side ring that includes a DMA-able
* buffer, the WR and RD indices, ring parameters such as max number of items
* an length of each items, and other miscellaneous runtime state.
* A msgbuf_ring may be used to represent a H2D or D2H common ring or a
* H2D TxPost ring as specified in the PCIE FullDongle Spec.
* Ring parameters are conveyed to the dongle, which maintains its own peer end
* ring state. Depending on whether the DMA Indices feature is supported, the
* host will update the WR/RD index in the DMA indices array in host memory or
* directly in dongle memory.
*/
typedef struct msgbuf_ring {
bool inited;
uint16 idx; /* ring id */
uint16 rd; /* read index */
uint16 curr_rd; /* read index for debug */
uint16 wr; /* write index */
uint16 max_items; /* maximum number of items in ring */
uint16 item_len; /* length of each item in the ring */
sh_addr_t base_addr; /* LITTLE ENDIAN formatted: base address */
dhd_dma_buf_t dma_buf; /* DMA-able buffer: pa, va, len, dmah, secdma */
uint32 seqnum; /* next expected item's sequence number */
#ifdef TXP_FLUSH_NITEMS
void *start_addr;
/* # of messages on ring not yet announced to dongle */
uint16 pend_items_count;
#ifdef AGG_H2D_DB
osl_atomic_t inflight;
#endif /* AGG_H2D_DB */
#endif /* TXP_FLUSH_NITEMS */
uint8 ring_type;
uint8 n_completion_ids;
bool create_pending;
uint16 create_req_id;
uint8 current_phase;
uint16 compeltion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED];
uchar name[RING_NAME_MAX_LENGTH];
uint32 ring_mem_allocated;
void *ring_lock;
struct msgbuf_ring *linked_ring; /* Ring Associated to metadata ring */
} msgbuf_ring_t;
#define DHD_RING_BGN_VA(ring) ((ring)->dma_buf.va)
#define DHD_RING_END_VA(ring) \
((uint8 *)(DHD_RING_BGN_VA((ring))) + \
(((ring)->max_items - 1) * (ring)->item_len))
#if (defined(BCM_ROUTER_DHD) && defined(HNDCTF))
/** D2H WLAN Rx Packet Chaining context */
typedef struct rxchain_info {
uint pkt_count;
uint ifidx;
void *pkthead;
void *pkttail;
uint8 *h_da; /* pointer to da of chain head */
uint8 *h_sa; /* pointer to sa of chain head */
uint8 h_prio; /* prio of chain head */
} rxchain_info_t;
#endif /* BCM_ROUTER_DHD && HNDCTF */
/* Legacy ring sizes for 1Gbps and lesser */
#define H2DRING_TXPOST_SIZE_V1 512u
#define H2DRING_HTPUT_TXPOST_SIZE_V1 512u /* Keep it same as H2DRING_TXPOST_SIZE_V1 */
#define D2HRING_TXCPL_SIZE_V1 1024u
#define H2DRING_RXPOST_SIZE_V1 512u
#define D2HRING_RXCPL_SIZE_V1 512u
#define H2DRING_CTRLPOST_SIZE_V1 64u
#define D2HRING_CTRLCPL_SIZE_V1 64u
#define RX_BUF_BURST_V1 32u /* Rx buffers for MSDU Data */
#define RX_BUFPOST_THRESHOLD_V1 32u /* Rxbuf post threshold */
/* Ring sizes version 2 for 2Gbps */
#define H2DRING_TXPOST_SIZE_V2 512u
#define H2DRING_HTPUT_TXPOST_SIZE_V2 2048u /* ONLY for 4 160 MHz BE flowrings */
#define D2HRING_TXCPL_SIZE_V2 2048u
#define H2DRING_RXPOST_SIZE_V2 2048u
#define D2HRING_RXCPL_SIZE_V2 1024u
#define H2DRING_CTRLPOST_SIZE_V2 128u
#define D2HRING_CTRLCPL_SIZE_V2 64u
#define RX_BUF_BURST_V2 64u /* Rx buffers for MSDU Data */
#define RX_BUFPOST_THRESHOLD_V2 64u /* Rxbuf post threshold */
int ring_size_version;
int ring_size_alloc_version;
uint h2d_max_txpost;
uint h2d_htput_max_txpost;
uint d2h_max_txcpl;
uint h2d_max_rxpost;
uint d2h_max_rxcpl;
uint h2d_max_ctrlpost;
uint d2h_max_ctrlcpl;
uint rx_buf_burst;
uint rx_bufpost_threshold;
#ifndef DHD_RX_CPL_POST_BOUND
#define DHD_RX_CPL_POST_BOUND 1024
#endif
#ifndef DHD_TX_POST_BOUND
#define DHD_TX_POST_BOUND 256
#endif
#ifndef DHD_CTRL_CPL_POST_BOUND
#define DHD_CTRL_CPL_POST_BOUND 64
#endif
#ifndef DHD_TX_CPL_BOUND
#define DHD_TX_CPL_BOUND 2048
#endif
uint dhd_rx_cpl_post_bound = DHD_RX_CPL_POST_BOUND;
uint dhd_tx_post_bound = DHD_TX_POST_BOUND;
uint dhd_tx_cpl_bound = DHD_TX_CPL_BOUND;
uint dhd_ctrl_cpl_post_bound = DHD_CTRL_CPL_POST_BOUND;
#ifdef AGG_H2D_DB
bool agg_h2d_db_enab = TRUE;
#define AGG_H2D_DB_TIMEOUT_USEC (1000u) /* 1 msec */
uint32 agg_h2d_db_timeout = AGG_H2D_DB_TIMEOUT_USEC;
#ifndef AGG_H2D_DB_INFLIGHT_THRESH
/* Keep inflight threshold same as txp_threshold */
#define AGG_H2D_DB_INFLIGHT_THRESH TXP_FLUSH_MAX_ITEMS_FLUSH_CNT
#endif /* !AGG_H2D_DB_INFLIGHT_THRESH */
uint32 agg_h2d_db_inflight_thresh = AGG_H2D_DB_INFLIGHT_THRESH;
#define DHD_NUM_INFLIGHT_HISTO_ROWS (14u)
#define DHD_INFLIGHT_HISTO_SIZE (sizeof(uint64) * DHD_NUM_INFLIGHT_HISTO_ROWS)
typedef struct _agg_h2d_db_info {
void *dhd;
struct hrtimer timer;
bool init;
uint32 direct_db_cnt;
uint32 timer_db_cnt;
uint64 *inflight_histo;
} agg_h2d_db_info_t;
#endif /* AGG_H2D_DB */
#define DHD_DEBUG_INVALID_PKTID
/** DHD protocol handle. Is an opaque type to other DHD software layers. */
typedef struct dhd_prot {
osl_t *osh; /* OSL handle */
uint16 rxbufpost_sz; /* Size of rx buffer posted to dongle */
uint16 rxbufpost_alloc_sz; /* Actual rx buffer packet allocated in the host */
uint16 rxbufpost;
uint16 rx_buf_burst;
uint16 rx_bufpost_threshold;
uint16 max_rxbufpost;
uint32 tot_rxbufpost;
uint32 tot_rxcpl;
uint16 max_eventbufpost;
uint16 max_ioctlrespbufpost;
uint16 max_tsbufpost;
uint16 max_infobufpost;
uint16 infobufpost;
uint16 cur_event_bufs_posted;
uint16 cur_ioctlresp_bufs_posted;
uint16 cur_ts_bufs_posted;
/* Flow control mechanism based on active transmits pending */
osl_atomic_t active_tx_count; /* increments/decrements on every packet tx/tx_status */
uint16 h2d_max_txpost;
uint16 h2d_htput_max_txpost;
uint16 txp_threshold; /* optimization to write "n" tx items at a time to ring */
/* MsgBuf Ring info: has a dhd_dma_buf that is dynamically allocated */
msgbuf_ring_t h2dring_ctrl_subn; /* H2D ctrl message submission ring */
msgbuf_ring_t h2dring_rxp_subn; /* H2D RxBuf post ring */
msgbuf_ring_t d2hring_ctrl_cpln; /* D2H ctrl completion ring */
msgbuf_ring_t d2hring_tx_cpln; /* D2H Tx complete message ring */
msgbuf_ring_t d2hring_rx_cpln; /* D2H Rx complete message ring */
msgbuf_ring_t *h2dring_info_subn; /* H2D info submission ring */
msgbuf_ring_t *d2hring_info_cpln; /* D2H info completion ring */
msgbuf_ring_t *d2hring_edl; /* D2H Enhanced Debug Lane (EDL) ring */
msgbuf_ring_t *h2d_flowrings_pool; /* Pool of preallocated flowings */
dhd_dma_buf_t flowrings_dma_buf; /* Contiguous DMA buffer for flowrings */
uint16 h2d_rings_total; /* total H2D (common rings + flowrings) */
uint32 rx_dataoffset;
dhd_mb_ring_t mb_ring_fn; /* called when dongle needs to be notified of new msg */
dhd_mb_ring_2_t mb_2_ring_fn; /* called when dongle needs to be notified of new msg */
/* ioctl related resources */
uint8 ioctl_state;
int16 ioctl_status; /* status returned from dongle */
uint16 ioctl_resplen;
dhd_ioctl_recieved_status_t ioctl_received;
uint curr_ioctl_cmd;
dhd_dma_buf_t retbuf; /* For holding ioctl response */
dhd_dma_buf_t ioctbuf; /* For holding ioctl request */
dhd_dma_buf_t d2h_dma_scratch_buf; /* For holding d2h scratch */
/* DMA-able arrays for holding WR and RD indices */
uint32 rw_index_sz; /* Size of a RD or WR index in dongle */
dhd_dma_buf_t h2d_dma_indx_wr_buf; /* Array of H2D WR indices */
dhd_dma_buf_t h2d_dma_indx_rd_buf; /* Array of H2D RD indices */
dhd_dma_buf_t d2h_dma_indx_wr_buf; /* Array of D2H WR indices */
dhd_dma_buf_t d2h_dma_indx_rd_buf; /* Array of D2H RD indices */
dhd_dma_buf_t h2d_ifrm_indx_wr_buf; /* Array of H2D WR indices for ifrm */
dhd_dma_buf_t host_bus_throughput_buf; /* bus throughput measure buffer */
dhd_dma_buf_t *flowring_buf; /* pool of flow ring buf */
#ifdef DHD_DMA_INDICES_SEQNUM
char *h2d_dma_indx_rd_copy_buf; /* Local copy of H2D WR indices array */
char *d2h_dma_indx_wr_copy_buf; /* Local copy of D2H WR indices array */
uint32 h2d_dma_indx_rd_copy_bufsz; /* H2D WR indices array size */
uint32 d2h_dma_indx_wr_copy_bufsz; /* D2H WR indices array size */
uint32 host_seqnum; /* Seqence number for D2H DMA Indices sync */
#endif /* DHD_DMA_INDICES_SEQNUM */
uint32 flowring_num;
d2h_sync_cb_t d2h_sync_cb; /* Sync on D2H DMA done: SEQNUM or XORCSUM */
#ifdef EWP_EDL
d2h_edl_sync_cb_t d2h_edl_sync_cb; /* Sync on EDL D2H DMA done: SEQNUM or XORCSUM */
#endif /* EWP_EDL */
ulong d2h_sync_wait_max; /* max number of wait loops to receive one msg */
ulong d2h_sync_wait_tot; /* total wait loops */
dhd_dmaxfer_t dmaxfer; /* for test/DMA loopback */
uint16 ioctl_seq_no;
uint16 data_seq_no; /* XXX this field is obsolete */
uint16 ioctl_trans_id;
void *pktid_ctrl_map; /* a pktid maps to a packet and its metadata */
void *pktid_rx_map; /* pktid map for rx path */
void *pktid_tx_map; /* pktid map for tx path */
bool metadata_dbg;
void *pktid_map_handle_ioctl;
#ifdef DHD_MAP_PKTID_LOGGING
void *pktid_dma_map; /* pktid map for DMA MAP */
void *pktid_dma_unmap; /* pktid map for DMA UNMAP */
#endif /* DHD_MAP_PKTID_LOGGING */
uint32 pktid_depleted_cnt; /* pktid depleted count */
/* netif tx queue stop count */
uint8 pktid_txq_stop_cnt;
/* netif tx queue start count */
uint8 pktid_txq_start_cnt;
uint64 ioctl_fillup_time; /* timestamp for ioctl fillup */
uint64 ioctl_ack_time; /* timestamp for ioctl ack */
uint64 ioctl_cmplt_time; /* timestamp for ioctl completion */
/* Applications/utilities can read tx and rx metadata using IOVARs */
uint16 rx_metadata_offset;
uint16 tx_metadata_offset;
#if (defined(BCM_ROUTER_DHD) && defined(HNDCTF))
rxchain_info_t rxchain; /* chain of rx packets */
#endif
#if defined(DHD_D2H_SOFT_DOORBELL_SUPPORT)
/* Host's soft doorbell configuration */
bcmpcie_soft_doorbell_t soft_doorbell[BCMPCIE_D2H_COMMON_MSGRINGS];
#endif /* DHD_D2H_SOFT_DOORBELL_SUPPORT */
/* Work Queues to be used by the producer and the consumer, and threshold
* when the WRITE index must be synced to consumer's workq
*/
dhd_dma_buf_t fw_trap_buf; /* firmware trap buffer */
#ifdef FLOW_RING_PREALLOC
/* pre-allocation htput ring buffer */
dhd_dma_buf_t htput_ring_buf[HTPUT_TOTAL_FLOW_RINGS];
/* pre-allocation folw ring(non htput rings) */
dhd_dma_buf_t flow_ring_buf[MAX_FLOW_RINGS];
#endif /* FLOW_RING_PREALLOC */
uint32 host_ipc_version; /* Host sypported IPC rev */
uint32 device_ipc_version; /* FW supported IPC rev */
uint32 active_ipc_version; /* Host advertised IPC rev */
dhd_dma_buf_t hostts_req_buf; /* For holding host timestamp request buf */
bool hostts_req_buf_inuse;
bool rx_ts_log_enabled;
bool tx_ts_log_enabled;
#ifdef DHD_HMAPTEST
uint32 hmaptest_rx_active;
uint32 hmaptest_rx_pktid;
char *hmap_rx_buf_va;
dmaaddr_t hmap_rx_buf_pa;
uint32 hmap_rx_buf_len;
uint32 hmaptest_tx_active;
uint32 hmaptest_tx_pktid;
char *hmap_tx_buf_va;
dmaaddr_t hmap_tx_buf_pa;
uint32 hmap_tx_buf_len;
dhd_hmaptest_t hmaptest; /* for hmaptest */
bool hmap_enabled; /* TRUE = hmap is enabled */
#endif /* DHD_HMAPTEST */
bool no_retry;
bool no_aggr;
bool fixed_rate;
dhd_dma_buf_t host_scb_buf; /* scb host offload buffer */
bool no_tx_resource;
uint32 txcpl_db_cnt;
#ifdef AGG_H2D_DB
agg_h2d_db_info_t agg_h2d_db_info;
#endif /* AGG_H2D_DB */
uint64 tx_h2d_db_cnt;
#ifdef DHD_DEBUG_INVALID_PKTID
uint8 ctrl_cpl_snapshot[D2HRING_CTRL_CMPLT_ITEMSIZE];
#endif /* DHD_DEBUG_INVALID_PKTID */
uint32 event_wakeup_pkt; /* Number of event wakeup packet rcvd */
uint32 rx_wakeup_pkt; /* Number of Rx wakeup packet rcvd */
uint32 info_wakeup_pkt; /* Number of info cpl wakeup packet rcvd */
msgbuf_ring_t *d2hring_md_cpl; /* D2H metadata completion ring */
/* no. which controls how many rx cpl/post items are processed per dpc */
uint32 rx_cpl_post_bound;
/*
* no. which controls how many tx post items are processed per dpc,
* i.e, how many tx pkts are posted to flowring from the bkp queue
* from dpc context
*/
uint32 tx_post_bound;
/* no. which controls how many tx cpl items are processed per dpc */
uint32 tx_cpl_bound;
/* no. which controls how many ctrl cpl/post items are processed per dpc */
uint32 ctrl_cpl_post_bound;
} dhd_prot_t;
#ifdef DHD_EWPR_VER2
#define HANG_INFO_BASE64_BUFFER_SIZE 640
#endif
#ifdef DHD_DUMP_PCIE_RINGS
static
int dhd_ring_write(dhd_pub_t *dhd, msgbuf_ring_t *ring, void *file,
const void *user_buf, unsigned long *file_posn);
#ifdef EWP_EDL
static
int dhd_edl_ring_hdr_write(dhd_pub_t *dhd, msgbuf_ring_t *ring, void *file, const void *user_buf,
unsigned long *file_posn);
#endif /* EWP_EDL */
#endif /* DHD_DUMP_PCIE_RINGS */
extern bool dhd_timesync_delay_post_bufs(dhd_pub_t *dhdp);
extern void dhd_schedule_dmaxfer_free(dhd_pub_t* dhdp, dmaxref_mem_map_t *dmmap);
/* Convert a dmaaddr_t to a base_addr with htol operations */
static INLINE void dhd_base_addr_htolpa(sh_addr_t *base_addr, dmaaddr_t pa);
/* APIs for managing a DMA-able buffer */
static int dhd_dma_buf_audit(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
static void dhd_dma_buf_reset(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
/* msgbuf ring management */
static int dhd_prot_allocate_bufs(dhd_pub_t *dhd, dhd_prot_t *prot);
static int dhd_prot_ring_attach(dhd_pub_t *dhd, msgbuf_ring_t *ring,
const char *name, uint16 max_items, uint16 len_item, uint16 ringid);
static void dhd_prot_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring);
static void dhd_prot_ring_reset(dhd_pub_t *dhd, msgbuf_ring_t *ring);
static void dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t *ring);
static void dhd_prot_process_fw_timestamp(dhd_pub_t *dhd, void* buf);
/* Pool of pre-allocated msgbuf_ring_t with DMA-able buffers for Flowrings */
static int dhd_prot_flowrings_pool_attach(dhd_pub_t *dhd);
static void dhd_prot_flowrings_pool_reset(dhd_pub_t *dhd);
static void dhd_prot_flowrings_pool_detach(dhd_pub_t *dhd);
/* Fetch and Release a flowring msgbuf_ring from flowring pool */
static msgbuf_ring_t *dhd_prot_flowrings_pool_fetch(dhd_pub_t *dhd,
uint16 flowid);
/* see also dhd_prot_flowrings_pool_release() in dhd_prot.h */
/* Producer: Allocate space in a msgbuf ring */
static void* dhd_prot_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring,
uint16 nitems, uint16 *alloced, bool exactly_nitems);
static void* dhd_prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems,
uint16 *alloced, bool exactly_nitems);
/* Consumer: Determine the location where the next message may be consumed */
static uint8* dhd_prot_get_read_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring,
uint32 *available_len, uint32 bound);
/* Producer (WR index update) or Consumer (RD index update) indication */
static void dhd_prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t *ring,
void *p, uint16 len);
#ifdef AGG_H2D_DB
static void dhd_prot_agg_db_ring_write(dhd_pub_t *dhd, msgbuf_ring_t * ring,
void* p, uint16 len);
static void dhd_prot_aggregate_db_ring_door_bell(dhd_pub_t *dhd, uint16 flowid, bool ring_db);
static void dhd_prot_txdata_aggr_db_write_flush(dhd_pub_t *dhd, uint16 flowid);
#endif /* AGG_H2D_DB */
static void dhd_prot_ring_doorbell(dhd_pub_t *dhd, uint32 value);
static void dhd_prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t *ring);
static INLINE int dhd_prot_dma_indx_alloc(dhd_pub_t *dhd, uint8 type,
dhd_dma_buf_t *dma_buf, uint32 bufsz);
/* Set/Get a RD or WR index in the array of indices */
/* See also: dhd_prot_dma_indx_init() */
void dhd_prot_dma_indx_set(dhd_pub_t *dhd, uint16 new_index, uint8 type,
uint16 ringid);
static uint16 dhd_prot_dma_indx_get(dhd_pub_t *dhd, uint8 type, uint16 ringid);
/* Locate a packet given a pktid */
static INLINE void *dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid, uint8 pkttype,
bool free_pktid);
/* Locate a packet given a PktId and free it. */
static INLINE void dhd_prot_packet_free(dhd_pub_t *dhd, void *pkt, uint8 pkttype, bool send);
static int dhd_msgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
void *buf, uint len, uint8 action);
static int dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
void *buf, uint len, uint8 action);
static int dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf);
static int dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd,
void *buf, int ifidx);
static void dhd_msgbuf_dump_iovar_name(dhd_pub_t *dhd);
/* Post buffers for Rx, control ioctl response and events */
static uint16 dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, uint8 msgid, uint32 max_to_post);
static void dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *pub);
static void dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *pub);
static void dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd, bool use_rsv_pktid);
static int dhd_prot_rxbuf_post(dhd_pub_t *dhd, uint16 count, bool use_rsv_pktid);
static int dhd_msgbuf_rxbuf_post_ts_bufs(dhd_pub_t *pub);
static void dhd_prot_return_rxbuf(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint32 pktid, uint32 rxcnt);
/* D2H Message handling */
static int dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8 *buf, uint32 len);
/* D2H Message handlers */
static void dhd_prot_noop(dhd_pub_t *dhd, void *msg);
static void dhd_prot_txstatus_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_ioctack_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_ringstatus_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_genstatus_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_event_process(dhd_pub_t *dhd, void *msg);
/* Loopback test with dongle */
static void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dma);
static int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len, uint srcdelay,
uint destdelay, dhd_dmaxfer_t *dma);
static void dhd_msgbuf_dmaxfer_process(dhd_pub_t *dhd, void *msg);
/* Flowring management communication with dongle */
static void dhd_prot_flow_ring_create_response_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_flow_ring_delete_response_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_flow_ring_flush_response_process(dhd_pub_t *dhd, void *msg);
static void dhd_prot_process_flow_ring_resume_response(dhd_pub_t *dhd, void* msg);
static void dhd_prot_process_flow_ring_suspend_response(dhd_pub_t *dhd, void* msg);
/* Monitor Mode */
#if defined(WL_MONITOR)
extern bool dhd_monitor_enabled(dhd_pub_t *dhd, int ifidx);
extern void dhd_rx_mon_pkt(dhd_pub_t *dhdp, host_rxbuf_cmpl_t* msg, void *pkt, int ifidx);
#if defined(DBG_PKT_MON)
extern void dhd_80211_mon_pkt(dhd_pub_t *dhdp, host_rxbuf_cmpl_t* msg, void *pkt, int ifidx);
#endif /* DBG_PKT_MON */
#endif /* WL_MONITOR */
/* Configure a soft doorbell per D2H ring */
static void dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd_pub_t *dhd);
static void dhd_prot_process_d2h_ring_config_complete(dhd_pub_t *dhd, void *msg);
static void dhd_prot_process_d2h_ring_create_complete(dhd_pub_t *dhd, void *buf);
#if !defined(BCM_ROUTER_DHD)
static void dhd_prot_process_h2d_ring_create_complete(dhd_pub_t *dhd, void *buf);
static void dhd_prot_process_infobuf_complete(dhd_pub_t *dhd, void* buf);
#endif /* !BCM_ROUTER_DHD */
static void dhd_prot_process_d2h_mb_data(dhd_pub_t *dhd, void* buf);
static void dhd_prot_detach_info_rings(dhd_pub_t *dhd);
#ifdef EWP_EDL
static void dhd_prot_detach_edl_rings(dhd_pub_t *dhd);
#endif
static void dhd_prot_detach_md_rings(dhd_pub_t *dhd);
static void dhd_prot_process_d2h_host_ts_complete(dhd_pub_t *dhd, void* buf);
static void dhd_prot_process_snapshot_complete(dhd_pub_t *dhd, void *buf);
#ifdef DHD_FLOW_RING_STATUS_TRACE
void dhd_dump_bus_flow_ring_status_isr_trace(dhd_bus_t *bus, struct bcmstrbuf *strbuf);
void dhd_dump_bus_flow_ring_status_dpc_trace(dhd_bus_t *bus, struct bcmstrbuf *strbuf);
#endif /* DHD_FLOW_RING_STATUS_TRACE */
#ifdef DHD_TX_PROFILE
extern bool dhd_protocol_matches_profile(uint8 *p, int plen, const
dhd_tx_profile_protocol_t *proto, bool is_host_sfhllc);
#endif /* defined(DHD_TX_PROFILE) */
static void dhd_update_rxstats(dhd_pub_t *dhd, host_rxbuf_cmpl_t *rxstatus);
typedef void (*dhd_msgbuf_func_t)(dhd_pub_t *dhd, void *msg);
/** callback functions for messages generated by the dongle */
#define MSG_TYPE_INVALID 0
static dhd_msgbuf_func_t table_lookup[DHD_PROT_FUNCS] = {
dhd_prot_noop, /* 0 is MSG_TYPE_INVALID */
dhd_prot_genstatus_process, /* MSG_TYPE_GEN_STATUS */
dhd_prot_ringstatus_process, /* MSG_TYPE_RING_STATUS */
NULL,
dhd_prot_flow_ring_create_response_process, /* MSG_TYPE_FLOW_RING_CREATE_CMPLT */
NULL,
dhd_prot_flow_ring_delete_response_process, /* MSG_TYPE_FLOW_RING_DELETE_CMPLT */
NULL,
dhd_prot_flow_ring_flush_response_process, /* MSG_TYPE_FLOW_RING_FLUSH_CMPLT */
NULL,
dhd_prot_ioctack_process, /* MSG_TYPE_IOCTLPTR_REQ_ACK */
NULL,
dhd_prot_ioctcmplt_process, /* MSG_TYPE_IOCTL_CMPLT */
NULL,
dhd_prot_event_process, /* MSG_TYPE_WL_EVENT */
NULL,
dhd_prot_txstatus_process, /* MSG_TYPE_TX_STATUS */
NULL,
NULL, /* MSG_TYPE_RX_CMPLT use dedicated handler */
NULL,
dhd_msgbuf_dmaxfer_process, /* MSG_TYPE_LPBK_DMAXFER_CMPLT */
NULL, /* MSG_TYPE_FLOW_RING_RESUME */
dhd_prot_process_flow_ring_resume_response, /* MSG_TYPE_FLOW_RING_RESUME_CMPLT */
NULL, /* MSG_TYPE_FLOW_RING_SUSPEND */
dhd_prot_process_flow_ring_suspend_response, /* MSG_TYPE_FLOW_RING_SUSPEND_CMPLT */
NULL, /* MSG_TYPE_INFO_BUF_POST */
#if defined(BCM_ROUTER_DHD)
NULL, /* MSG_TYPE_INFO_BUF_CMPLT */
#else
dhd_prot_process_infobuf_complete, /* MSG_TYPE_INFO_BUF_CMPLT */
#endif /* BCM_ROUTER_DHD */
NULL, /* MSG_TYPE_H2D_RING_CREATE */
NULL, /* MSG_TYPE_D2H_RING_CREATE */
#if defined(BCM_ROUTER_DHD)
NULL, /* MSG_TYPE_H2D_RING_CREATE_CMPLT */
#else
dhd_prot_process_h2d_ring_create_complete, /* MSG_TYPE_H2D_RING_CREATE_CMPLT */
#endif /* BCM_ROUTER_DHD */
dhd_prot_process_d2h_ring_create_complete, /* MSG_TYPE_D2H_RING_CREATE_CMPLT */
NULL, /* MSG_TYPE_H2D_RING_CONFIG */
NULL, /* MSG_TYPE_D2H_RING_CONFIG */
NULL, /* MSG_TYPE_H2D_RING_CONFIG_CMPLT */
dhd_prot_process_d2h_ring_config_complete, /* MSG_TYPE_D2H_RING_CONFIG_CMPLT */
NULL, /* MSG_TYPE_H2D_MAILBOX_DATA */
dhd_prot_process_d2h_mb_data, /* MSG_TYPE_D2H_MAILBOX_DATA */
NULL, /* MSG_TYPE_TIMSTAMP_BUFPOST */
NULL, /* MSG_TYPE_HOSTTIMSTAMP */
dhd_prot_process_d2h_host_ts_complete, /* MSG_TYPE_HOSTTIMSTAMP_CMPLT */