-
Notifications
You must be signed in to change notification settings - Fork 95
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
JAL handling procedure #39
Comments
Hi, I still have this question, but now JAL and JALR are passing. I add a mux in the RVFI and when JAL comes, it performs a forwarding data from EX to WB. Delivering the correct destination address. These strategi allow me to find a bug in JALR calculation, do you think is a valid approach? Thanks |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
I have been working with the riscv-formal for a couple of months now.
Arithmetic, load and store checks are passing but I want to ask you what would be the procedure for a JAL?, at the end of the pipe I have 2 PC values without importance when JAL comes.
I see the correct PC in the pipe.
But how could I tell that the data is not ready yet? if I put the jump trigger signal in the valid the output is warmup!
I am working with a SIIO 5-stage pipeline core.
Thank you for a great tool.
The text was updated successfully, but these errors were encountered: