Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

clearing fields #247

Open
cuber2116 opened this issue Jan 19, 2025 · 4 comments
Open

clearing fields #247

cuber2116 opened this issue Jan 19, 2025 · 4 comments
Labels
question Further information is requested

Comments

@cuber2116
Copy link

cuber2116 commented Jan 19, 2025

addrmap my_addrmap {
    reg target_register { regwidth = 32; accesswidth = 32; // The register to be cleared
        field {
            name = "target_field";
            sw = rw;       // Read-only for software
            hw = rw;      // Read-write for hardware
            reset = 0x0;
        } target_field[1];      // 32-bit field
    };
    reg  w1c_register{  regwidth = 32; accesswidth = 32; // The W1C register
        field {
            name = "w1c_another_field";
            sw = rw;      // Write-1-to-Clear for software
            hw = rw;        // Read-only for hardware
            reset = 0x0;
            //onwrite = target_register.target_field-> woclr;
        } w1c_another_field[1];      // 32-bit field
    };
    target_register tar_reg @0x0;
    w1c_register w1c_reg  @0x4;
};

Every time a 1 is written in the w1c_another_field, the target_field gets cleared.

How do I achieve this?

@amykyta3
Copy link
Member

Assign a reference to the trigger field to the target's hwclr property.
Then using the singlepulse you can make the trigger auto-clear itself.

addrmap my_addrmap {
    reg target_register {
        field {
            sw = rw;
            hw = rw;
        } target_field[1] = 0;
    };

    reg  w1c_register{
        field {
            sw = rw;
            hw = na;
            singlepulse; // Always self-clears to 0
        } w1c_another_field[1] = 0;
    };

    target_register tar_reg @0x0;
    w1c_register w1c_reg  @0x4;

    // Clear the target if trigger register is 1
    tar_reg.target_field->hwclr = w1c_reg.w1c_another_field;
};

@amykyta3 amykyta3 added the question Further information is requested label Jan 22, 2025
@cuber2116
Copy link
Author

Thank you so much!
I also wanted to ask if there was a way to have to an interrupt signal which will be the bitwise OR of all the interrupt fields?

@amykyta3
Copy link
Member

SystemRDL natively supports interrupts and the implicit OR you describe. See section 17 of the SystemRDL 2.0 spec. They have some pretty good examples of how interrupts work.

@Samrat-03
Copy link

I have a question. In the example code, the implicit OR is done by "global_int.global_int->next = master_int->intr;" but in my case there are no global or master interrupt registers. I just have a few lower-level leaf interrupts and a top-level interrupt signal. So, can I use the same method for interrupt signal? Something like - interrupt_signal -> next = leaf_int -> intr.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
question Further information is requested
Projects
None yet
Development

No branches or pull requests

3 participants