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Technology_characterization.md

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Technology characterization

These steps generate lookup tables for buffered or non-buffered wire segments delimited by flip-flops. The lookup tables are used as building blocks for clock tree construction and store information about delay, power and slew of the wire segments.
A buffered wire segment delimited by two flip-flops

*** These steps are required per foundry/IP enablement, since the enablement is visible only under NDA, and often readable only by foundry-qualified tools. Please refer to OpenROAD Flow and Notes for a better understanding of supported technologies and current limitations / assumptions.

  • Change directory to genLUT folder.
$ cd ../genLUT

  • Update the following variables in template/config.tcl accordingly:

    • list_lib - Path to you library files.
      • E.g.: set list_lib "path/to/my/library.lib"
    • cap_unit - Must set to 1 if your library has pF as capacitance unit or 1000 if your library has fF as capacitance unit.
      • E.g.: set cap_unit 1
    • time_unit - Must set to 1 if your library has ns as timing unit or 1000 if your library has ps as timing unit.
      • E.g.: set time_unit 1
    • bufTypes - List of standard cells to be used as clock buffers.
      • E.g.: set bufTypes "BUF_X1 BUF_X2 BUF_X4 BUF_X16 BUF_X32"
    • Q_ffpin - Name of the output data pin of the library flip-flops.
      • E.g.: set Q_ffpin "Q"
    • D_ffpin - Name of the input data pin of the library flip-flips.
      • E.g.: set D_ffpin "D"
    • buff_inPin - Name of the input pin of the library buffers.
      • E.g: set buff_inPin "A"
    • buff_outPin - Name of the output pin of the library buffers.
      • E.g.: set buff_outPin "Y"
    • clk_pin - Clock signal pin name of the library flip-flips.
      • E.g.: set clk_pin "CK
    • bufName - Library buffer to be used as a placeholder at the beginning of the characterization.
      • E.g.: set bufName "BUF_X16"
    • FFName - Library flip-flop to be used in the end of the wire during characterization.
      • E.g.: set FFName "FF_X2"
    • cellHeight - Height of your library cells in um.
      • E.g.: set cellHeight "0.5"
    • cap_per_unit_len - Capacitance per unit length of your technology. Use your technology units and update only the value after the keyword expr
      • E.g.: set cap_per_unit_len [expr (0.8 / 1000) * $cap_unit ]
    • res_per_unit_len - Resistance per unit length of your technology. Use your technology units and update only the value after the keyword expr
      • set res_per_unit_len [expr (0.9 / 1000) * $cap_unit ] # Assumes cap and res multipliers are the same
    • initial_cap_interval - used for rounding to the nearest capacitance value during characterization for fine-grained change of output load
      • E.g: set initial_cap_interval 0.001 #Assumes the capacitance units are in fF
    • final_cap_interval - used for rounding to the nearest capacitance value during characterization for coarse-grained change of output load.
      • E.g: set final_cap_interval 0.005 #Assumes the capacitance units are in fF
  • We encourage you to DO NOT change the following variables unless you REALLY know what you are doing.

    • maxSlew, inputSlew, slewInter - max, min and step for slew in characterization scripts.

      • E.g.: set maxSlew [expr 0.060 * $time_unit]
      • E.g.: set inputSlew [expr 0.005 * $time_unit]
      • E.g.: set slewInter [expr 0.005 * $time_unit]

    • outloadNum, baseLoad, loadInter - Number of loads, min load value and step for the characterization scripts. For the last two, only change the value after expr using your library units.

      • E.g.: set outLoadNum 34
      • E.g.: set baseLoad [expr 0.005 * $cap_unit]
      • E.g.: set loadInter [ expr 0.005 * $cap_unit]

  • Run the characterization script, run_all.tcl (a valid OpenSTA binary under genLUT is required).

  • After run_all.tcl script has finished, make sure that a file named XX.lut exists under each generated folder. The characterization folders have the naming convention: test_XX_YY_NDR, where XX is the dist, YY is the unit_dist and NDR is the non-default rule. When characterizing for larger values of dist (e.g. dist=80 um), on a single core the expected runtime is around 1 hour or less depending on your local setup.

  • Edit variable lutList in genLUTOpt2.tcl with the paths of the XX.lut files

  • Run the genLUTOpt2.tcl script:

$ ./genLUTOpt2.tcl > concat.lut
  • Run prep_lut.tcl
$ ./prep_lut.tcl concat.lut
  • Copy the result files, sol_list.txt and lut.txt, to TritonCTS/src/tech folder, renaming them according to your technology node.

For example, if you are using ST28, you would rename as:

$ cp sol_list.txt ../../src/tech/sol_list-28.txt

$ cp lut.txt ../../src/tech/lut-28.txt

For example, if you are using TSMC16, you would rename as:

$ cp sol_list.txt ../../src/tech/sol_list-16.txt

$ cp lut.txt ../../src/tech/lut-16.txt
  • To check your setup, please verify the following:
    • Folders test_XX_YY_NDR
    • Non-empty XX.lut file under each test_XX_YY_NDR folder.
    • Non-empty sol_list-XX.txt file under ../../src/tech
    • Non-empty lut-XX.txt file under ../../src/tech

(We provide examples of technology characterization files for 45nm OpenPDK here.)