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kernel.cu
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/*
* Copyright (C) 2024 Forefront Industries, Ltd.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cuda_fp16.h"
#include <cuda_pipeline.h>
#include <stdio.h>
#include <cmath>
#include <tuple>
#include "configs.cu"
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define load(x) __ldcg(x)
#define store(x, value) __stcs(x, value)
#define div_ru(a, b) (a + b - 1) / b
#define div_rd(a, b) a / b
#define VOLATILE
#define DEBUG
#define CUDA_DEVICE_INLINE __device__ __forceinline__
#define ENABLE_L2_PREFETCH true
#define LAYOUT_C true
#define LAYOUT_F false
#define TRANSFORM_N true
#define TRANSFORM_T false
#define QUANTIZED true
#define NOT_QUANTIZED false
#define ACC_MODE_HALF 16
#define ACC_MODE_FLOAT 32
typedef bool MATRIX_LAYOUT;
typedef bool MATRIX_TRANSFORM;
typedef bool MATRIX_QUANTIZE_STATUS;
using typeA = uint8_t;
using typeB = half;
using typeCode = half;
using typeAbsMax = half;
using typeAcc = float;
constexpr int accMode = 32;
constexpr int accBytes = 4; // accumulate in fp32
typedef struct __builtin_align__(8)
{
half x1, x2, x3, x4;
}
half4;
typedef struct __builtin_align__(16)
{
half x1, x2, x3, x4, x5, x6, x7, x8;
}
half8;
typedef struct __builtin_align__(16)
{
unsigned char x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16;
}
uchar16;
typedef struct __builtin_align__(16)
{
char x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16;
}
char16;
typedef struct
{
int x;
} Coord1D;
typedef struct
{
int x, y;
} Coord2D;
typedef struct
{
int x, y, z;
} Coord3D;
typedef struct
{
int x, y, z, t;
} Coord4D;
typedef struct
{
int x, y, z, t, u;
} Coord5D;
typedef union
{
signed char as_int8[1];
unsigned char as_uint8[1];
} Data1B;
typedef union
{
short as_int16[1];
unsigned short as_uint16[1];
signed char as_int8[2];
unsigned char as_uint8[2];
half as_half[1];
} Data2B;
typedef union
{
int as_int32[1];
unsigned int as_uint32[1];
short as_int16[2];
unsigned short as_uint16[2];
signed char as_int8[4];
unsigned char as_uint8[4];
float as_float[1];
half2 as_half2[1];
half as_half[2];
} Data4B;
typedef union
{
long long as_int64[1];
unsigned long long as_uint64[1];
int as_int32[2];
unsigned int as_uint32[2];
short as_int16[4];
unsigned short as_uint16[4];
signed char as_int8[8];
unsigned char as_uint8[8];
double as_double[1];
half4 as_half4[1];
float2 as_float2[1];
float as_float[2];
half2 as_half2[2];
half as_half[4];
} Data8B;
typedef union
{
uchar16 as_uchar16[1];
char16 as_char16[1];
long long as_int64[2];
unsigned long long as_uint64[2];
int as_int32[4];
unsigned int as_uint32[4];
short as_int16[8];
unsigned short as_uint16[8];
signed char as_int8[16];
unsigned char as_uint8[16];
half8 as_half8[1];
double as_double[2];
half4 as_half4[2];
float2 as_float2[2];
float as_float[4];
half2 as_half2[4];
half as_half[8];
} Data16B;
#if (!defined(__clang__) && __CUDACC_VER_MAJOR__ == 10 && __CUDACC_VER_MINOR__ >= 2)
extern "C"
{
__device__ uint32_t __nvvm_get_smem_pointer(void *);
}
#endif
CUDA_DEVICE_INLINE
unsigned get_smem_pointer(void const *ptr)
{
#if (!defined(__clang__) && defined(__CUDA_ARCH__) && __CUDACC_VER_MAJOR__ >= 11)
return static_cast<unsigned>(__cvta_generic_to_shared(ptr));
#elif (!defined(__clang__) && defined(__CUDA_ARCH__) && __CUDACC_VER_MAJOR__ == 10 && __CUDACC_VER_MINOR__ >= 2)
return __nvvm_get_smem_pointer(ptr);
#elif defined(__CUDA_ARCH__)
uint32_t smem_ptr;
asm(
"{ .reg .u64 smem_ptr; cvta.to.shared.u64 smem_ptr, %1; cvt.u32.u64 %0, smem_ptr; }\n"
: "=r"(smem_ptr) : "l"(ptr));
return smem_ptr;
#else
return 0;
#endif
}
CUDA_DEVICE_INLINE
void ldsm_x1_C(
void *srcPtr,
Data4B dest[1])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x1.m8n8.shared.b16 {%0}, [%1];"
: "=r"(dest[0].as_int32[0])
: "r"(srcAddr));
}
CUDA_DEVICE_INLINE
void ldsm_x2_C(
void *srcPtr,
Data4B dest[2])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x2.m8n8.shared.b16 {%0, %1}, [%2];"
: "=r"(dest[0].as_int32[0]), "=r"(dest[1].as_int32[0])
: "r"(srcAddr));
}
CUDA_DEVICE_INLINE
void ldsm_x4_C(
void *srcPtr,
Data4B dest[4])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x4.m8n8.shared.b16 {%0, %1, %2, %3}, [%4];"
: "=r"(dest[0].as_int32[0]), "=r"(dest[1].as_int32[0]), "=r"(dest[2].as_int32[0]), "=r"(dest[3].as_int32[0])
: "r"(srcAddr));
}
CUDA_DEVICE_INLINE
void ldsm_x1_F(
void *srcPtr,
Data4B dest[1])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x1.trans.m8n8.shared.b16 {%0}, [%1];"
: "=r"(dest[0].as_int32[0])
: "r"(srcAddr));
}
CUDA_DEVICE_INLINE
void ldsm_x2_F(
void *srcPtr,
Data4B dest[2])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x2.trans.m8n8.shared.b16 {%0, %1}, [%2];"
: "=r"(dest[0].as_int32[0]), "=r"(dest[1].as_int32[0])
: "r"(srcAddr));
}
CUDA_DEVICE_INLINE
void ldsm_x4_F(
void *srcPtr,
Data4B dest[4])
{
unsigned int srcAddr = get_smem_pointer(srcPtr);
asm volatile(
"ldmatrix.sync.aligned.x4.trans.m8n8.shared.b16 {%0, %1, %2, %3}, [%4];"
: "=r"(dest[0].as_int32[0]), "=r"(dest[1].as_int32[0]), "=r"(dest[2].as_int32[0]), "=r"(dest[3].as_int32[0])
: "r"(srcAddr));
}
template <int matrixCount, MATRIX_LAYOUT layout>
CUDA_DEVICE_INLINE void ldsm(
void *srcPtr,
Data4B dest[matrixCount])
{
if (matrixCount == 1 && layout == LAYOUT_C)
ldsm_x1_C(srcPtr, dest);
else if (matrixCount == 2 && layout == LAYOUT_C)
ldsm_x2_C(srcPtr, dest);
else if (matrixCount == 4 && layout == LAYOUT_C)
ldsm_x4_C(srcPtr, dest);
else if (matrixCount == 1 && layout == LAYOUT_F)
ldsm_x1_F(srcPtr, dest);
else if (matrixCount == 2 && layout == LAYOUT_F)
ldsm_x2_F(srcPtr, dest);
else if (matrixCount == 4 && layout == LAYOUT_F)
ldsm_x4_F(srcPtr, dest);
}
template <int size>
CUDA_DEVICE_INLINE void ldgsts_ca(
void const *srcPtr,
void *destPtr,
bool p = true)
{
unsigned smemPtr = get_smem_pointer(destPtr);
asm volatile(
"{\n"
" .reg .pred p;\n"
" setp.ne.b32 p, %0, 0;\n"
" @p cp.async.ca.shared.global [%1], [%2], %3;\n"
"}\n" ::"r"((int)p),
"r"(smemPtr), "l"(srcPtr), "n"(size));
}
template <int size>
CUDA_DEVICE_INLINE void ldgsts_ca_prefetch(
void const *srcPtr,
void *destPtr,
bool p = true)
{
unsigned smemPtr = get_smem_pointer(destPtr);
asm volatile(
"{\n"
" .reg .pred p;\n"
" setp.ne.b32 p, %0, 0;\n"
" @p cp.async.ca.shared.global.L2::128B [%1], [%2], %3;\n"
"}\n" ::"r"((int)p),
"r"(smemPtr), "l"(srcPtr), "n"(size));
}
template <int size>
CUDA_DEVICE_INLINE void ldgsts_cg(
void const *srcPtr,
void *destPtr,
bool p = true)
{
unsigned smemPtr = get_smem_pointer(destPtr);
asm volatile(
"{\n"
" .reg .pred p;\n"
" setp.ne.b32 p, %0, 0;\n"
" @p cp.async.cg.shared.global [%1], [%2], %3;\n"
"}\n" ::"r"((int)p),
"r"(smemPtr), "l"(srcPtr), "n"(size));
}
template <int size>
CUDA_DEVICE_INLINE void ldgsts_cg_prefetch(
void const *srcPtr,
void *destPtr,
bool p = true)
{
unsigned smemPtr = get_smem_pointer(destPtr);
asm volatile(
"{\n"
" .reg .pred p;\n"
" setp.ne.b32 p, %0, 0;\n"
" @p cp.async.cg.shared.global.L2::128B [%1], [%2], %3;\n"
"}\n" ::"r"((int)p),
"r"(smemPtr), "l"(srcPtr), "n"(size));
}
template <int size, bool cacheAllways, bool prefetchL2>
CUDA_DEVICE_INLINE void ldgsts(
// void const* srcPtr,
void const *srcPtr,
void *destPtr,
bool p = true)
{
if (cacheAllways)
if (prefetchL2)
ldgsts_ca_prefetch<size>(srcPtr, destPtr, p);
else
ldgsts_ca<size>(srcPtr, destPtr, p);
else if (prefetchL2)
ldgsts_cg_prefetch<size>(srcPtr, destPtr, p);
else
ldgsts_cg<size>(srcPtr, destPtr, p);
}
CUDA_DEVICE_INLINE
void mma_m16n8k16_fp16_CF(
Data4B fragA[4],
Data4B fragB[2],
Data4B accumulator[2])
{
asm volatile(
"mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {%0, %1}, {%2, %3, %4, %5}, {%6, %7}, {%0, %1};"
: "+r"(accumulator[0].as_int32[0]), "+r"(accumulator[1].as_int32[0])
: "r"(fragA[0].as_int32[0]), "r"(fragA[1].as_int32[0]), "r"(fragA[2].as_int32[0]), "r"(fragA[3].as_int32[0]), "r"(fragB[0].as_int32[0]), "r"(fragB[1].as_int32[0]));
}
CUDA_DEVICE_INLINE
void mma_m16n8k8_fp16_CF(
Data4B fragA[2],
Data4B fragB[1],
Data4B accumulator[2])
{
asm volatile(
"mma.sync.aligned.m16n8k8.row.col.f16.f16.f16.f16 {%0, %1}, {%2, %3}, {%4}, {%0, %1};"
: "+r"(accumulator[0].as_int32[0]), "+r"(accumulator[1].as_int32[0])
: "r"(fragA[0].as_int32[0]), "r"(fragA[1].as_int32[0]), "r"(fragB[0].as_int32[0]));
}
CUDA_DEVICE_INLINE
void mma_m16n8k8_fp32_CF(
Data4B fragA[2],
Data4B fragB[1],
Data4B accumulator[4])
{
asm volatile(
"mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {%0, %1, %2, %3}, {%4, %5}, {%6}, {%0, %1, %2, %3};"
: "+r"(accumulator[0].as_int32[0]), "+r"(accumulator[1].as_int32[0]), "+r"(accumulator[2].as_int32[0]), "+r"(accumulator[3].as_int32[0])
: "r"(fragA[0].as_int32[0]), "r"(fragA[1].as_int32[0]), "r"(fragB[0].as_int32[0]));
}
CUDA_DEVICE_INLINE
void mma_m16n8k16_fp32_CF(
Data4B fragA[4],
Data4B fragB[2],
Data4B accumulator[4])
{
asm volatile(
"mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};"
: "+r"(accumulator[0].as_int32[0]), "+r"(accumulator[1].as_int32[0]), "+r"(accumulator[2].as_int32[0]), "+r"(accumulator[3].as_int32[0])
: "r"(fragA[0].as_int32[0]), "r"(fragA[1].as_int32[0]), "r"(fragA[2].as_int32[0]), "r"(fragA[3].as_int32[0]), "r"(fragB[0].as_int32[0]), "r"(fragB[1].as_int32[0]));
}
#define mma_param_is_equal(left, p1, p2, p3, p4, p5) \
(left.mmaSizeM == p1 && \
left.mmaSizeN == p2 && \
left.mmaSizeK == p3 && \
left.layoutA == p4 && \
left.layoutB == p5)
typedef struct
{
int mmaSizeM, mmaSizeN, mmaSizeK;
MATRIX_LAYOUT layoutA, layoutB;
} MmaParam;
template <
int mmaSizeM,
int mmaSizeN,
int mmaSizeK,
MATRIX_LAYOUT layoutA,
MATRIX_LAYOUT layoutB,
int outPrecision>
CUDA_DEVICE_INLINE void mma(
Data4B fragA[(mmaSizeM / 8) * (mmaSizeK / 8)],
Data4B fragB[(mmaSizeN / 8) * (mmaSizeK / 8)],
Data4B accumulator[(mmaSizeM / 8) * (mmaSizeN / 8) * (accMode == 32 ? 2 : 1)])
{
constexpr MmaParam param = {mmaSizeM, mmaSizeN, mmaSizeK, layoutA, layoutB};
if constexpr (accMode == 32)
{
if (mma_param_is_equal(param, 16, 8, 8, LAYOUT_C, LAYOUT_F))
mma_m16n8k8_fp32_CF(fragA, fragB, accumulator);
else if (mma_param_is_equal(param, 16, 8, 16, LAYOUT_C, LAYOUT_F))
mma_m16n8k16_fp32_CF(fragA, fragB, accumulator);
}
else if constexpr (accMode == 16)
{
if (mma_param_is_equal(param, 16, 8, 8, LAYOUT_C, LAYOUT_F))
mma_m16n8k8_fp16_CF(fragA, fragB, accumulator);
else if (mma_param_is_equal(param, 16, 8, 16, LAYOUT_C, LAYOUT_F))
mma_m16n8k16_fp16_CF(fragA, fragB, accumulator);
}
}
template <
int mmaSizeM,
int mmaSizeN,
int mmaSizeK,
MATRIX_LAYOUT layoutA,
MATRIX_LAYOUT layoutB,
int outPrecision>
CUDA_DEVICE_INLINE void ntcmma(
Data4B fragA[(mmaSizeM / 8) * (mmaSizeK / 8)],
Data4B fragB[(mmaSizeN / 8) * (mmaSizeK / 8)],
Data4B accumulator[(mmaSizeM / 8) * (mmaSizeN / 8) * (outPrecision == 32 ? 2 : 1)])
{
int tid = threadIdx.x;
int lid = tid % 32;
constexpr Coord3D mmaMatrixCount = {mmaSizeM / 8, mmaSizeN / 8, mmaSizeK / 8};
Coord2D laneIdx4 = {lid / 4, lid % 4};
#pragma unroll
for (int om = 0; om < mmaMatrixCount.x; om++)
{
#pragma unroll
for (int on = 0; on < mmaMatrixCount.y; on++)
{
#pragma unroll
for (int ok = 0; ok < mmaMatrixCount.z; ok++)
{
half2 currentFragA = fragA[om * mmaMatrixCount.z + ok].as_half2[0];
half2 currentFragB = fragB[on * mmaMatrixCount.z + ok].as_half2[0];
#pragma unroll
for (int im = 0; im < 8; im++)
{
#pragma unroll
for (int in = 0; in < 8; in++)
{
#pragma unroll
for (int ik = 0; ik < 4; ik++)
{
half2 swappedFragA = __shfl_sync(0xffffffff, currentFragA, im * 4 + ik);
half2 swappedFragB = __shfl_sync(0xffffffff, currentFragB, in * 4 + ik);
accumulator[om * mmaMatrixCount.y + on].as_half2[0] = __hfma2(swappedFragA, swappedFragB, accumulator[om * mmaMatrixCount.y + on].as_half2[0]);
}
}
}
}
}
}
}
template <
typename T>
class SmemTensor0D
{
public:
VOLATILE T *endPtr;
VOLATILE T *startPtr;
CUDA_DEVICE_INLINE
SmemTensor0D(VOLATILE void *smemPtr)
: startPtr(reinterpret_cast<T *>(smemPtr)), endPtr(reinterpret_cast<T *>(smemPtr))
{
}
CUDA_DEVICE_INLINE
T get()
{
return startPtr[0];
}
CUDA_DEVICE_INLINE
T *get_ptr()
{
return startPtr;
}
CUDA_DEVICE_INLINE
void set(const T value)
{
startPtr[0] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U
get_reinterpreted()
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return newPtr[0];
}
template <typename U>
CUDA_DEVICE_INLINE void set_reinterpreted(U value)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
newPtr[0] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U *
get_ptr_reinterpreted()
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return &newPtr[0];
}
};
template <
typename T,
int ShapeX>
class SmemTensor1D
{
public:
VOLATILE T *endPtr;
VOLATILE T *startPtr;
CUDA_DEVICE_INLINE
SmemTensor1D(VOLATILE void *smemPtr)
: startPtr(reinterpret_cast<T *>(smemPtr)), endPtr(reinterpret_cast<T *>(smemPtr) + shape().x)
{
}
CUDA_DEVICE_INLINE
T get(int x)
{
return startPtr[x];
}
CUDA_DEVICE_INLINE
T *get_ptr(int x)
{
return &startPtr[x];
}
CUDA_DEVICE_INLINE
void set(int x, const T value)
{
startPtr[x] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U
get_reinterpreted(int x)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return newPtr[x];
}
template <typename U>
CUDA_DEVICE_INLINE void set_reinterpreted(int x, U value)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
newPtr[x] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U *
get_ptr_reinterpreted(int x)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return &newPtr[x];
}
CUDA_DEVICE_INLINE
static constexpr Coord1D shape()
{
return {ShapeX};
}
};
template <
typename T,
int ShapeX,
int ShapeY>
class SmemTensor2D
{
public:
VOLATILE T *endPtr;
VOLATILE T *startPtr;
CUDA_DEVICE_INLINE
SmemTensor2D(VOLATILE void *smemPtr)
: startPtr(reinterpret_cast<T *>(smemPtr)), endPtr(reinterpret_cast<T *>(smemPtr) + shape().x * shape().y)
{
}
CUDA_DEVICE_INLINE
T get(int x, int y)
{
return startPtr[x * stride().x + y];
}
CUDA_DEVICE_INLINE
T *get_ptr(int x, int y)
{
return &startPtr[x * stride().x + y];
}
CUDA_DEVICE_INLINE
void set(int x, int y, const T value)
{
startPtr[x * stride().x + y] = value;
}
CUDA_DEVICE_INLINE
SmemTensor1D<T, ShapeY> get_child(int x)
{
SmemTensor1D<T, ShapeY> child(
&startPtr[x * stride().x]);
return child;
}
template <typename U>
CUDA_DEVICE_INLINE
U
get_reinterpreted(int x, int y)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return newPtr[(x * stride().x) * sizeof(T) / sizeof(U) +
y];
}
template <typename U>
CUDA_DEVICE_INLINE void set_reinterpreted(int x, int y, U value)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
newPtr[(x * stride().x) * sizeof(T) / sizeof(U) +
y] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U *
get_ptr_reinterpreted(int x, int y)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return &newPtr[(x * stride().x) * sizeof(T) / sizeof(U) +
y];
}
CUDA_DEVICE_INLINE
static constexpr Coord2D shape()
{
return {ShapeX, ShapeY};
}
CUDA_DEVICE_INLINE
static constexpr Coord1D stride()
{
return {ShapeY};
}
};
template <
typename T,
int ShapeX,
int ShapeY,
int ShapeZ>
class SmemTensor3D
{
public:
VOLATILE T *endPtr;
VOLATILE T *startPtr;
CUDA_DEVICE_INLINE
SmemTensor3D(VOLATILE void *smemPtr)
: startPtr(reinterpret_cast<T *>(smemPtr)), endPtr(reinterpret_cast<T *>(smemPtr) + shape().x * shape().y * shape().z)
{
}
CUDA_DEVICE_INLINE
T get(int x, int y, int z)
{
return startPtr[x * stride().x + y * stride().y + z];
}
CUDA_DEVICE_INLINE
T *get_ptr(int x, int y, int z)
{
return &startPtr[x * stride().x + y * stride().y + z];
}
CUDA_DEVICE_INLINE
void set(int x, int y, int z, const T value)
{
startPtr[x * stride().x + y * stride().y + z] = value;
}
CUDA_DEVICE_INLINE
SmemTensor2D<T, ShapeY, ShapeZ> get_child(int x)
{
SmemTensor2D<T, ShapeY, ShapeZ> child(
&startPtr[x * stride().x]);
return child;
}
CUDA_DEVICE_INLINE
SmemTensor1D<T, ShapeZ> get_child(int x, int y)
{
SmemTensor1D<T, ShapeZ> child(
&startPtr[x * stride().x + y * stride().y]);
return child;
}
template <typename U>
CUDA_DEVICE_INLINE
U
get_reinterpreted(int x, int y, int z)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return newPtr[(x * stride().x +
y * stride().y) *
sizeof(T) / sizeof(U) +
z];
}
template <typename U>
CUDA_DEVICE_INLINE void set_reinterpreted(int x, int y, int z, U value)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
newPtr[(x * stride().x +
y * stride().y) *
sizeof(T) / sizeof(U) +
z] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U *
get_ptr_reinterpreted(int x, int y, int z)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return &newPtr[(x * stride().x +
y * stride().y) *
sizeof(T) / sizeof(U) +
z];
}
CUDA_DEVICE_INLINE
static constexpr Coord3D shape()
{
return {ShapeX, ShapeY, ShapeZ};
}
CUDA_DEVICE_INLINE
static constexpr Coord2D stride()
{
return {ShapeY * ShapeZ, ShapeZ};
}
};
template <
typename T,
int ShapeX,
int ShapeY,
int ShapeZ,
int ShapeT>
class SmemTensor4D
{
public:
VOLATILE T *endPtr;
VOLATILE T *startPtr;
CUDA_DEVICE_INLINE
SmemTensor4D(VOLATILE void *smemPtr)
: startPtr(reinterpret_cast<T *>(smemPtr)), endPtr(&reinterpret_cast<T *>(smemPtr)[shape().x * shape().y * shape().z * shape().t])
{
}
CUDA_DEVICE_INLINE
T get(int x, int y, int z, int t)
{
return startPtr[x * stride().x +
y * stride().y +
z * stride().z +
t];
}
CUDA_DEVICE_INLINE
T *get_ptr(int x, int y, int z, int t)
{
return &startPtr[x * stride().x +
y * stride().y +
z * stride().z +
t];
}
CUDA_DEVICE_INLINE
void set(int x, int y, int z, int t, const T value)
{
startPtr[x * stride().x +
y * stride().y +
z * stride().z +
t] = value;
}
CUDA_DEVICE_INLINE
SmemTensor3D<T, ShapeY, ShapeZ, ShapeT> get_child(int x)
{
SmemTensor3D<T, ShapeY, ShapeZ, ShapeT> child(
&startPtr[x * stride().x]);
return child;
}
CUDA_DEVICE_INLINE
SmemTensor2D<T, ShapeZ, ShapeT> get_child(int x, int y)
{
SmemTensor2D<T, ShapeZ, ShapeT> child(
&startPtr[x * stride().x + y * stride().y]);
return child;
}
CUDA_DEVICE_INLINE
SmemTensor1D<T, ShapeT> get_child(int x, int y, int z)
{
SmemTensor1D<T, ShapeT> child(
&startPtr[x * stride().x + y * stride().y + z * stride().z]);
return child;
}
template <typename U>
CUDA_DEVICE_INLINE
U
get_reinterpreted(int x, int y, int z, int t)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return newPtr[(x * stride().x +
y * stride().y +
z * stride().z) *
sizeof(T) / sizeof(U) +
t];
}
template <typename U>
CUDA_DEVICE_INLINE void set_reinterpreted(int x, int y, int z, int t, U value)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
newPtr[(x * stride().x +
y * stride().y +
z * stride().z) *
sizeof(T) / sizeof(U) +
t] = value;
}
template <typename U>
CUDA_DEVICE_INLINE
U *
get_ptr_reinterpreted(int x, int y, int z, int t)
{
U *newPtr = reinterpret_cast<U *>(startPtr);
return &newPtr[(x * stride().x +
y * stride().y +
z * stride().z) *
sizeof(T) / sizeof(U) +
t];
}
CUDA_DEVICE_INLINE
static constexpr Coord4D shape()
{
return {ShapeX, ShapeY, ShapeZ, ShapeT};
}
CUDA_DEVICE_INLINE
static constexpr Coord3D stride()
{
return {
ShapeY * ShapeZ * ShapeT,
ShapeZ * ShapeT,
ShapeT};
}
};
template <
typename T,
int TileN, // non contiguous dimention
int TileC, // contiguous dimention
int AccessSize // number of type T elements to read per access. Should be 8 fp16 or 16 int8 for mma.sync
// MATRIX_LAYOUT Layout
>
class TileIndexConverter
{
public:
CUDA_DEVICE_INLINE
TileIndexConverter()
{
}
CUDA_DEVICE_INLINE
Coord2D convert(const Coord2D logicalIdx)
{
if (splits() == 1)
{
return {
logicalIdx.x,
(logicalIdx.y + (logicalIdx.x % indent_count()) * AccessSize) % physical_shape().y};
}
else
{
Coord2D tempIdx = {
logicalIdx.x % physical_shape().x,
(logicalIdx.y + (logicalIdx.x / physical_shape().x) * logical_shape().y)};
return {
tempIdx.x,
(tempIdx.y + (tempIdx.x % indent_count()) * AccessSize) % physical_shape().y};
}
}
CUDA_DEVICE_INLINE
Coord2D convert_reinterpreted(const Coord2D logicalIdx, const int newSize)
{
Coord2D result = convert({logicalIdx.x, logicalIdx.y * newSize / sizeof(T)});
result.y = result.y * sizeof(T) / newSize;
return result;
}
CUDA_DEVICE_INLINE
int convert_to_offset(const Coord2D logicalIdx)
{
Coord2D physicalIdx = convert(logicalIdx);
return physicalIdx.x * physical_shape().y + physicalIdx.y;
}
CUDA_DEVICE_INLINE
int convert_to_offset_reinterpreted(const Coord2D logicalIdx, const int newSize)
{
Coord2D physicalIdx = convert_reinterpreted(logicalIdx, newSize);
return physicalIdx.x * (physical_shape_bytes().y / newSize) + physicalIdx.y;
}
CUDA_DEVICE_INLINE
static constexpr int splits()
{
return logical_shape_bytes().y < 128 ? 128 / logical_shape_bytes().y : 1;