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ngzhianngzhian
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[spectext] Add double precision conversion
Instructions were added in #383. Consolidate conversion operations (vcvtop) more, merging int-int widening operations. Drive-by fix extmul definition in syntax (shouldn't include the shape).
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8 files changed

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‎document/core/appendix/gen-index-instructions.py‎

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -446,10 +446,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\I16X8.\BITMASK', r'\hex{FD}~~132', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
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Instruction(r'\I16X8.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~133', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
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Instruction(r'\I16X8.\NARROW\K{\_i16x8\_u}', r'\hex{FD}~~134', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
449-
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
450-
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
451-
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
452-
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
449+
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
450+
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
451+
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
452+
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
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Instruction(r'\I16X8.\VSHL', r'\hex{FD}~~139', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
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Instruction(r'\I16X8.\VSHR\K{\_s}', r'\hex{FD}~~140', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
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Instruction(r'\I16X8.\VSHR\K{\_u}', r'\hex{FD}~~141', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
@@ -478,10 +478,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
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Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}', r'\hex{FD}~~165', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
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Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}', r'\hex{FD}~~166', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
481-
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
482-
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
483-
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
484-
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
481+
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
482+
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
483+
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
484+
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
485485
Instruction(r'\I32X4.\VSHL', r'\hex{FD}~~171', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
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Instruction(r'\I32X4.\VSHR\K{\_s}', r'\hex{FD}~~172', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
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Instruction(r'\I32X4.\VSHR\K{\_u}', r'\hex{FD}~~173', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
@@ -500,10 +500,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\I64X2.\VABS', r'\hex{FD}~~162', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
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Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
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Instruction(r'\I64X2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
503-
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
504-
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
505-
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
506-
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
503+
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
504+
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
505+
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
506+
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vcvtop'),
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Instruction(r'\I64X2.\VSHL', r'\hex{FD}~~203', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
508508
Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
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Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
@@ -537,10 +537,16 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\F64X2.\VPMIN', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'),
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Instruction(r'\F64X2.\VPMAX', r'\hex{FD}~~246', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'),
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Instruction(r'\F64X2.\VMAX', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'),
540-
Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_s}', r'\hex{FD}~~248', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_s'),
541-
Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_u}', r'\hex{FD}~~249', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_u'),
542-
Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_s}', r'\hex{FD}~~250', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-convert_s'),
543-
Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_u}', r'\hex{FD}~~251', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-convert_u'),
540+
Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_s}', r'\hex{FD}~~248', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_s'),
541+
Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_u}', r'\hex{FD}~~249', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'),
542+
Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_s}', r'\hex{FD}~~250', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'),
543+
Instruction(r'\F32X4.\CONVERT\K{\_i32x4\_u}', r'\hex{FD}~~251', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'),
544+
Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}', r'\hex{FD}~~85', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_s'),
545+
Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~86', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'),
546+
Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~83', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'),
547+
Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~84', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'),
548+
Instruction(r'\F32X4.\VDEMOTE\K{\_f64x2\_zero}', r'\hex{FD}~~87', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-demote'),
549+
Instruction(r'\F64X2.\VPROMOTE\K{\_low\_f32x4}', r'\hex{FD}~~105', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-promote'),
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]
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def ColumnWidth(n):

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