openmips_min_sopc.syr

Release 13.2 - xst O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Reading design: openmips_min_sopc.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "openmips_min_sopc.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "openmips_min_sopc"
Output Format                      : NGC
Target Device                      : xc6slx16-3-csg324

---- Source Options
Top Module Name                    : openmips_min_sopc
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\regfile.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <regfile>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\pc_reg.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <pc_reg>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\mem_wb.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 21.
Parsing module <mem_wb>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\mem.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <mem>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\if_id.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <if_id>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\id_ex.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <id_ex>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\id.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <id>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\hilo_reg.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 21.
Parsing module <hilo_reg>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\ex_mem.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <ex_mem>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\ex.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <ex>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\div.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 21.
Parsing module <div>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\ctrl.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 21.
Parsing module <ctrl>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\ipcore_dir\inst_rom.v\" into library work
Parsing module <inst_rom>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\openmips.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 22.
Parsing module <openmips>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\mux8t1_4.v\" into library work
Parsing module <mux8t1_4>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\mux4t1_4.v\" into library work
Parsing module <mux4t1_4>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\decoder_7seg.v\" into library work
Parsing module <decoder_7seg>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\clk_div.v\" into library work
Parsing module <clk_div>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\anti_jitter.v\" into library work
Parsing module <anti_jitter>.
Analyzing Verilog file \"E:\Workspace\ISE\OpenMIPS\code\openmips_min_sopc.v\" into library work
Parsing verilog file "E:\Workspace\ISE\OpenMIPS\code\/defines.v" included at line 21.
Parsing module <openmips_min_sopc>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <openmips_min_sopc>.
WARNING:HDLCompiler:1127 - "E:\Workspace\ISE\OpenMIPS\code\openmips_min_sopc.v" Line 47: Assignment to clk ignored, since the identifier is never used

Elaborating module <openmips>.

Elaborating module <pc_reg>.

Elaborating module <ctrl>.

Elaborating module <if_id>.

Elaborating module <id>.
WARNING:HDLCompiler:1127 - "E:\Workspace\ISE\OpenMIPS\code\id.v" Line 77: Assignment to instvalid ignored, since the identifier is never used

Elaborating module <regfile>.

Elaborating module <hilo_reg>.

Elaborating module <id_ex>.

Elaborating module <ex>.

Elaborating module <ex_mem>.

Elaborating module <mem>.

Elaborating module <mem_wb>.

Elaborating module <div>.
WARNING:HDLCompiler:413 - "E:\Workspace\ISE\OpenMIPS\code\div.v" Line 92: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:1127 - "E:\Workspace\ISE\OpenMIPS\code\openmips_min_sopc.v" Line 55: Assignment to rom_ce ignored, since the identifier is never used

Elaborating module <inst_rom>.
WARNING:HDLCompiler:1499 - "E:\Workspace\ISE\OpenMIPS\ipcore_dir\inst_rom.v" Line 39: Empty module <inst_rom> remains a black box.

Elaborating module <decoder_7seg>.

Elaborating module <mux8t1_4>.

Elaborating module <mux4t1_4>.

Elaborating module <anti_jitter>.
WARNING:HDLCompiler:1127 - "E:\Workspace\ISE\OpenMIPS\code\openmips_min_sopc.v" Line 90: Assignment to btn_out ignored, since the identifier is never used

Elaborating module <clk_div>.
WARNING:HDLCompiler:1127 - "E:\Workspace\ISE\OpenMIPS\code\openmips_min_sopc.v" Line 98: Assignment to clk_cpu ignored, since the identifier is never used

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <openmips_min_sopc>.
    Related source file is "e:/workspace/ise/openmips/code/openmips_min_sopc.v".
INFO:Xst:3210 - "e:/workspace/ise/openmips/code/openmips_min_sopc.v" line 50: Output port <rom_ce_o> of the instance <openmips> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "e:/workspace/ise/openmips/code/openmips_min_sopc.v" line 86: Output port <btn_out> of the instance <anti_jitter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "e:/workspace/ise/openmips/code/openmips_min_sopc.v" line 86: Output port <btn_pulse> of the instance <anti_jitter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "e:/workspace/ise/openmips/code/openmips_min_sopc.v" line 94: Output port <clk_cpu> of the instance <clk_div> is unconnected or connected to loadless signal.
    Found 8-bit 4-to-1 multiplexer for signal <led> created at line 105.
    Summary:
	inferred   1 Multiplexer(s).
Unit <openmips_min_sopc> synthesized.

Synthesizing Unit <openmips>.
    Related source file is "e:/workspace/ise/openmips/code/openmips.v".
    Summary:
	no macro.
Unit <openmips> synthesized.

Synthesizing Unit <pc_reg>.
    Related source file is "e:/workspace/ise/openmips/code/pc_reg.v".
WARNING:Xst:647 - Input <stall<5:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <pc>.
    Found 1-bit register for signal <ce>.
    Found 32-bit adder for signal <pc[31]_GND_3_o_add_6_OUT> created at line 50.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <pc_reg> synthesized.

Synthesizing Unit <ctrl>.
    Related source file is "e:/workspace/ise/openmips/code/ctrl.v".
    Summary:
	inferred   2 Multiplexer(s).
Unit <ctrl> synthesized.

Synthesizing Unit <if_id>.
    Related source file is "e:/workspace/ise/openmips/code/if_id.v".
WARNING:Xst:647 - Input <stall<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <stall<3:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <id_inst>.
    Found 32-bit register for signal <id_pc>.
    Summary:
	inferred  64 D-type flip-flop(s).
Unit <if_id> synthesized.

Synthesizing Unit <id>.
    Related source file is "e:/workspace/ise/openmips/code/id.v".
    Found 32-bit adder for signal <pc_plus_8> created at line 73.
    Found 32-bit adder for signal <pc_plus_4> created at line 74.
    Found 32-bit adder for signal <imm_sll2_signedext[31]_pc_plus_4[31]_add_68_OUT> created at line 468.
    Found 32-bit comparator equal for signal <reg1_o[31]_reg2_o[31]_equal_68_o> created at line 467
    Found 5-bit comparator equal for signal <reg1_addr_o[4]_ex_wd_i[4]_equal_206_o> created at line 677
    Found 5-bit comparator equal for signal <reg1_addr_o[4]_mem_wd_i[4]_equal_209_o> created at line 679
    Found 5-bit comparator equal for signal <reg2_addr_o[4]_ex_wd_i[4]_equal_220_o> created at line 693
    Found 5-bit comparator equal for signal <reg2_addr_o[4]_mem_wd_i[4]_equal_223_o> created at line 695
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred   5 Comparator(s).
	inferred  81 Multiplexer(s).
Unit <id> synthesized.

Synthesizing Unit <regfile>.
    Related source file is "e:/workspace/ise/openmips/code/regfile.v".
    Found 1024-bit register for signal <n0068[1023:0]>.
    Found 32-bit 32-to-1 multiplexer for signal <raddr1[4]_regs[31][31]_wide_mux_46_OUT> created at line 62.
    Found 32-bit 32-to-1 multiplexer for signal <raddr2[4]_regs[31][31]_wide_mux_57_OUT> created at line 76.
    Found 5-bit comparator equal for signal <raddr1[4]_waddr[4]_equal_43_o> created at line 59
    Found 5-bit comparator equal for signal <raddr2[4]_waddr[4]_equal_54_o> created at line 73
    Summary:
	inferred 1024 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  42 Multiplexer(s).
Unit <regfile> synthesized.

Synthesizing Unit <hilo_reg>.
    Related source file is "e:/workspace/ise/openmips/code/hilo_reg.v".
    Found 32-bit register for signal <lo>.
    Found 32-bit register for signal <hi>.
    Summary:
	inferred  64 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <hilo_reg> synthesized.

Synthesizing Unit <id_ex>.
    Related source file is "e:/workspace/ise/openmips/code/id_ex.v".
WARNING:Xst:647 - Input <stall<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <stall<4:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <ex_alusel>.
    Found 32-bit register for signal <ex_reg1>.
    Found 32-bit register for signal <ex_reg2>.
    Found 5-bit register for signal <ex_wd>.
    Found 1-bit register for signal <ex_wreg>.
    Found 32-bit register for signal <ex_link_address>.
    Found 1-bit register for signal <ex_is_in_delayslot>.
    Found 1-bit register for signal <is_in_delayslot_o>.
    Found 8-bit register for signal <ex_aluop>.
    Summary:
	inferred 115 D-type flip-flop(s).
Unit <id_ex> synthesized.

Synthesizing Unit <ex>.
    Related source file is "e:/workspace/ise/openmips/code/ex.v".
WARNING:Xst:647 - Input <is_in_delayslot_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 6-bit subtractor for signal <PWR_11_o_GND_10_o_sub_61_OUT> created at line 217.
    Found 32-bit adder for signal <result_sum> created at line 100.
    Found 32-bit adder for signal <reg1_i[31]_GND_10_o_add_16_OUT> created at line 127.
    Found 32-bit adder for signal <reg2_i[31]_GND_10_o_add_24_OUT> created at line 132.
    Found 64-bit adder for signal <hilo_temp[63]_GND_10_o_add_155_OUT> created at line 324.
    Found 64-bit adder for signal <hilo_temp_i[63]_HI[31]_add_162_OUT> created at line 350.
    Found 64-bit adder for signal <mulres[63]_GND_10_o_add_171_OUT> created at line 356.
    Found 32x32-bit multiplier for signal <hilo_temp> created at line 135.
    Found 32-bit shifter logical left for signal <reg2_i[31]_reg1_i[4]_shift_left_58_OUT> created at line 211
    Found 32-bit shifter logical right for signal <reg2_i[31]_reg1_i[4]_shift_right_59_OUT> created at line 214
    Found 32-bit shifter logical left for signal <reg2_i[31]_PWR_11_o_shift_left_61_OUT> created at line 217
    Found 32-bit 8-to-1 multiplexer for signal <wdata_o> created at line 450.
    Found 32-bit 4-to-1 multiplexer for signal <_n0581> created at line 142.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<62>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<61>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<60>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<59>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<58>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<57>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<56>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<55>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<54>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<53>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<52>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<51>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<50>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<49>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<48>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<47>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<46>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<45>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<44>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<43>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<42>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<41>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<40>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<39>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<38>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<37>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<36>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<35>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<34>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<33>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<32>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <cnt_o<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <cnt_o<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <stallreq_for_madd_msub>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<63>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<62>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<61>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<60>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<59>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<58>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<57>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<56>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<55>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<54>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<53>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<52>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<51>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<50>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<49>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<48>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<47>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<46>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<45>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<44>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<43>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<42>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<41>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<40>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<39>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<38>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<37>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<36>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<35>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<34>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<33>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<32>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp1<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <hilo_temp_o<63>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit comparator greater for signal <reg1_i[31]_reg2_i[31]_LessThan_9_o> created at line 119
    Summary:
	inferred   1 Multiplier(s).
	inferred   7 Adder/Subtractor(s).
	inferred 131 Latch(s).
	inferred   1 Comparator(s).
	inferred 124 Multiplexer(s).
	inferred   3 Combinational logic shifter(s).
Unit <ex> synthesized.

Synthesizing Unit <ex_mem>.
    Related source file is "e:/workspace/ise/openmips/code/ex_mem.v".
WARNING:Xst:647 - Input <stall<0:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <stall<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <mem_wreg>.
    Found 32-bit register for signal <mem_wdata>.
    Found 32-bit register for signal <mem_hi>.
    Found 32-bit register for signal <mem_lo>.
    Found 1-bit register for signal <mem_whilo>.
    Found 64-bit register for signal <hilo_o>.
    Found 2-bit register for signal <cnt_o>.
    Found 5-bit register for signal <mem_wd>.
    Summary:
	inferred 169 D-type flip-flop(s).
Unit <ex_mem> synthesized.

Synthesizing Unit <mem>.
    Related source file is "e:/workspace/ise/openmips/code/mem.v".
    Summary:
	inferred   6 Multiplexer(s).
Unit <mem> synthesized.

Synthesizing Unit <mem_wb>.
    Related source file is "e:/workspace/ise/openmips/code/mem_wb.v".
WARNING:Xst:647 - Input <stall<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <wb_wreg>.
    Found 32-bit register for signal <wb_wdata>.
    Found 32-bit register for signal <wb_hi>.
    Found 32-bit register for signal <wb_lo>.
    Found 1-bit register for signal <wb_whilo>.
    Found 5-bit register for signal <wb_wd>.
    Summary:
	inferred 103 D-type flip-flop(s).
Unit <mem_wb> synthesized.

Synthesizing Unit <div>.
    Related source file is "e:/workspace/ise/openmips/code/div.v".
    Found 1-bit register for signal <ready_o>.
    Found 64-bit register for signal <result_o>.
    Found 65-bit register for signal <dividend>.
    Found 6-bit register for signal <cnt>.
    Found 32-bit register for signal <divisor>.
    Found 2-bit register for signal <state>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 3                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 33-bit subtractor for signal <div_temp> created at line 43.
    Found 32-bit adder for signal <opdata1_i[31]_GND_147_o_add_9_OUT> created at line 60.
    Found 32-bit adder for signal <opdata2_i[31]_GND_147_o_add_14_OUT> created at line 65.
    Found 6-bit adder for signal <cnt[5]_GND_147_o_add_28_OUT> created at line 92.
    Found 32-bit adder for signal <dividend[31]_GND_147_o_add_32_OUT> created at line 97.
    Found 32-bit adder for signal <dividend[64]_GND_147_o_add_36_OUT> created at line 102.
    Summary:
	inferred   6 Adder/Subtractor(s).
	inferred 168 D-type flip-flop(s).
	inferred 106 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <div> synthesized.

Synthesizing Unit <decoder_7seg>.
    Related source file is "e:/workspace/ise/openmips/code/decoder_7seg.v".
    Found 16x8-bit Read Only RAM for signal <segment>
    Summary:
	inferred   1 RAM(s).
Unit <decoder_7seg> synthesized.

Synthesizing Unit <mux8t1_4>.
    Related source file is "e:/workspace/ise/openmips/code/mux8t1_4.v".
    Found 4-bit 8-to-1 multiplexer for signal <o> created at line 28.
    Summary:
	inferred   1 Multiplexer(s).
Unit <mux8t1_4> synthesized.

Synthesizing Unit <mux4t1_4>.
    Related source file is "e:/workspace/ise/openmips/code/mux4t1_4.v".
    Found 4x4-bit Read Only RAM for signal <o>
    Summary:
	inferred   1 RAM(s).
Unit <mux4t1_4> synthesized.

Synthesizing Unit <anti_jitter>.
    Related source file is "e:/workspace/ise/openmips/code/anti_jitter.v".
    Found 8-bit register for signal <sw_temp>.
    Found 32-bit register for signal <counter>.
    Found 1-bit register for signal <pulse>.
    Found 5-bit register for signal <btn_out>.
    Found 8-bit register for signal <sw_ok>.
    Found 5-bit register for signal <btn_pulse>.
    Found 5-bit register for signal <btn_temp>.
    Found 32-bit adder for signal <counter[31]_GND_152_o_add_4_OUT> created at line 41.
    Found 5-bit comparator not equal for signal <n0000> created at line 37
    Found 8-bit comparator not equal for signal <n0002> created at line 37
    Found 32-bit comparator greater for signal <counter[31]_GND_152_o_LessThan_4_o> created at line 40
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  64 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <anti_jitter> synthesized.

Synthesizing Unit <clk_div>.
    Related source file is "e:/workspace/ise/openmips/code/clk_div.v".
    Found 32-bit register for signal <clkdiv>.
    Found 32-bit adder for signal <clkdiv[31]_GND_153_o_add_0_OUT> created at line 33.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <clk_div> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 16x8-bit single-port Read Only RAM                    : 1
 4x4-bit single-port Read Only RAM                     : 1
# Multipliers                                          : 1
 32x32-bit multiplier                                  : 1
# Adders/Subtractors                                   : 19
 32-bit adder                                          : 13
 33-bit subtractor                                     : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 1
 64-bit adder                                          : 3
# Registers                                            : 43
 1-bit register                                        : 10
 1024-bit register                                     : 1
 2-bit register                                        : 1
 3-bit register                                        : 1
 32-bit register                                       : 17
 5-bit register                                        : 6
 6-bit register                                        : 1
 64-bit register                                       : 2
 65-bit register                                       : 1
 8-bit register                                        : 3
# Latches                                              : 131
 1-bit latch                                           : 131
# Comparators                                          : 11
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 2
 5-bit comparator equal                                : 6
 5-bit comparator not equal                            : 1
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 367
 1-bit 2-to-1 multiplexer                              : 155
 2-bit 2-to-1 multiplexer                              : 1
 3-bit 2-to-1 multiplexer                              : 5
 32-bit 2-to-1 multiplexer                             : 174
 32-bit 32-to-1 multiplexer                            : 2
 32-bit 4-to-1 multiplexer                             : 1
 32-bit 8-to-1 multiplexer                             : 1
 4-bit 8-to-1 multiplexer                              : 1
 5-bit 2-to-1 multiplexer                              : 7
 6-bit 2-to-1 multiplexer                              : 4
 64-bit 2-to-1 multiplexer                             : 8
 65-bit 2-to-1 multiplexer                             : 4
 8-bit 2-to-1 multiplexer                              : 3
 8-bit 4-to-1 multiplexer                              : 1
# Logic shifters                                       : 3
 32-bit shifter logical left                           : 2
 32-bit shifter logical right                          : 1
# FSMs                                                 : 1
# Xors                                                 : 4
 1-bit xor2                                            : 3
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <ipcore_dir/inst_rom.ngc>.
Loading core <inst_rom> for timing and area information for instance <inst_rom>.
WARNING:Xst:2677 - Node <sw_ok_0> of sequential type is unconnected in block <anti_jitter>.
WARNING:Xst:2677 - Node <sw_ok_2> of sequential type is unconnected in block <anti_jitter>.
WARNING:Xst:2677 - Node <sw_ok_3> of sequential type is unconnected in block <anti_jitter>.
WARNING:Xst:2677 - Node <sw_ok_4> of sequential type is unconnected in block <anti_jitter>.
WARNING:Xst:2677 - Node <sw_ok_5> of sequential type is unconnected in block <anti_jitter>.

Synthesizing (advanced) Unit <anti_jitter>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <anti_jitter> synthesized (advanced).

Synthesizing (advanced) Unit <clk_div>.
The following registers are absorbed into counter <clkdiv>: 1 register on signal <clkdiv>.
Unit <clk_div> synthesized (advanced).

Synthesizing (advanced) Unit <decoder_7seg>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_segment> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <digit>         |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <segment>       |          |
    -----------------------------------------------------------------------
Unit <decoder_7seg> synthesized (advanced).

Synthesizing (advanced) Unit <mux4t1_4>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_o> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 4-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <sel>           |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <o>             |          |
    -----------------------------------------------------------------------
Unit <mux4t1_4> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 16x8-bit single-port distributed Read Only RAM        : 1
 4x4-bit single-port distributed Read Only RAM         : 1
# Multipliers                                          : 1
 32x32-bit multiplier                                  : 1
# Adders/Subtractors                                   : 17
 32-bit adder                                          : 11
 33-bit subtractor                                     : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 1
 64-bit adder                                          : 3
# Counters                                             : 2
 32-bit up counter                                     : 2
# Registers                                            : 1772
 Flip-Flops                                            : 1772
# Comparators                                          : 11
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 2
 5-bit comparator equal                                : 6
 5-bit comparator not equal                            : 1
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 489
 1-bit 2-to-1 multiplexer                              : 281
 2-bit 2-to-1 multiplexer                              : 1
 3-bit 2-to-1 multiplexer                              : 5
 32-bit 2-to-1 multiplexer                             : 170
 32-bit 32-to-1 multiplexer                            : 2
 32-bit 4-to-1 multiplexer                             : 1
 32-bit 8-to-1 multiplexer                             : 1
 4-bit 8-to-1 multiplexer                              : 1
 5-bit 2-to-1 multiplexer                              : 7
 6-bit 2-to-1 multiplexer                              : 4
 64-bit 2-to-1 multiplexer                             : 8
 65-bit 2-to-1 multiplexer                             : 4
 8-bit 2-to-1 multiplexer                              : 3
 8-bit 4-to-1 multiplexer                              : 1
# Logic shifters                                       : 3
 32-bit shifter logical left                           : 2
 32-bit shifter logical right                          : 1
# FSMs                                                 : 1
# Xors                                                 : 4
 1-bit xor2                                            : 3
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <openmips/div/FSM_0> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 10    | 01
 01    | 10
 11    | 11
-------------------
WARNING:Xst:2677 - Node <clk_div/clkdiv_20> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_21> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_22> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_23> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_24> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_25> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_26> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_27> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_28> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_29> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_30> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <clk_div/clkdiv_31> of sequential type is unconnected in block <openmips_min_sopc>.
INFO:Xst:2261 - The FF/Latch <cnt_o_0> in Unit <ex> is equivalent to the following FF/Latch, which will be removed : <stallreq_for_madd_msub> 
WARNING:Xst:2016 - Found a loop when searching source clock on port 'Mmux__n05861:O'
Last warning will be issued only once.

Optimizing unit <openmips_min_sopc> ...

Optimizing unit <anti_jitter> ...

Optimizing unit <openmips> ...

Optimizing unit <if_id> ...

Optimizing unit <pc_reg> ...

Optimizing unit <regfile> ...

Optimizing unit <hilo_reg> ...

Optimizing unit <id_ex> ...

Optimizing unit <ex_mem> ...

Optimizing unit <mem_wb> ...

Optimizing unit <div> ...

Optimizing unit <id> ...

Optimizing unit <ex> ...
WARNING:Xst:2677 - Node <anti_jitter/pulse> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/sw_ok_5> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/sw_ok_4> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/sw_ok_3> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/sw_ok_2> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/sw_ok_0> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_out_4> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_out_3> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_out_2> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_out_1> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_out_0> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_pulse_4> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_pulse_3> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_pulse_2> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_pulse_1> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <anti_jitter/btn_pulse_0> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <openmips/pc_reg/ce> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <openmips/id_ex/ex_is_in_delayslot> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:2677 - Node <openmips/id_ex/is_in_delayslot_o> of sequential type is unconnected in block <openmips_min_sopc>.
WARNING:Xst:1710 - FF/Latch <openmips/regfile/regs_31_1014> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1013> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1012> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1011> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1010> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1009> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1008> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1007> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1006> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1005> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1004> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1003> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1002> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1001> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1000> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_999> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_998> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_997> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_996> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_995> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_994> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_993> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_992> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_31> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_30> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_29> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_28> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_27> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_26> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_25> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_24> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_23> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_22> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_21> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_20> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_19> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_18> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <anti_jitter/counter_17> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1023> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1022> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1021> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1020> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1019> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1018> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1017> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1016> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <openmips/regfile/regs_31_1015> (without init value) has a constant value of 0 in block <openmips_min_sopc>. This FF/Latch will be trimmed during the optimization process.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block openmips_min_sopc, actual ratio is 61.
FlipFlop openmips/id_ex/ex_aluop_0 has been replicated 1 time(s)
FlipFlop openmips/id_ex/ex_aluop_1 has been replicated 1 time(s)
FlipFlop openmips/id_ex/ex_aluop_3 has been replicated 1 time(s)
FlipFlop openmips/id_ex/ex_aluop_4 has been replicated 1 time(s)
FlipFlop openmips/id_ex/ex_aluop_7 has been replicated 1 time(s)
FlipFlop openmips/id_ex/ex_reg1_0 has been replicated 2 time(s)
FlipFlop openmips/id_ex/ex_reg1_1 has been replicated 2 time(s)
FlipFlop openmips/id_ex/ex_reg1_2 has been replicated 2 time(s)
FlipFlop openmips/id_ex/ex_reg1_3 has been replicated 2 time(s)
FlipFlop openmips/id_ex/ex_reg1_4 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1774
 Flip-Flops                                            : 1774

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : openmips_min_sopc.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 5839
#      GND                         : 2
#      INV                         : 193
#      LUT1                        : 126
#      LUT2                        : 223
#      LUT3                        : 1354
#      LUT4                        : 255
#      LUT5                        : 418
#      LUT6                        : 1956
#      MUXCY                       : 620
#      MUXF7                       : 86
#      VCC                         : 1
#      XORCY                       : 605
# FlipFlops/Latches                : 1904
#      FD                          : 13
#      FDC                         : 20
#      FDE                         : 106
#      FDR                         : 68
#      FDRE                        : 1567
#      LDC                         : 66
#      LDE_1                       : 64
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 13
#      OBUF                        : 20
# DSPs                             : 4
#      DSP48A1                     : 4

Device utilization summary:
---------------------------

Selected Device : 6slx16csg324-3 


Slice Logic Utilization: 
 Number of Slice Registers:            1904  out of  18224    10%  
 Number of Slice LUTs:                 4525  out of   9112    49%  
    Number used as Logic:              4525  out of   9112    49%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   5771
   Number with an unused Flip Flop:    3867  out of   5771    67%  
   Number with an unused LUT:          1246  out of   5771    21%  
   Number of fully used LUT-FF pairs:   658  out of   5771    11%  
   Number of unique control sets:        17

IO Utilization: 
 Number of IOs:                          34
 Number of bonded IOBs:                  34  out of    232    14%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                3  out of     16    18%  
 Number of DSP48A1s:                      4  out of     32    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------+------------------------------------+-------+
Clock Signal                                   | Clock buffer(FF name)              | Load  |
-----------------------------------------------+------------------------------------+-------+
clk_100mhz                                     | BUFGP                              | 1774  |
sw<7>                                          | IBUF+BUFG                          | 64    |
openmips/ex/_n0586(openmips/ex/Mmux__n058611:O)| BUFG(*)(openmips/ex/hilo_temp_o_63)| 66    |
-----------------------------------------------+------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 21.580ns (Maximum Frequency: 46.340MHz)
   Minimum input arrival time before clock: 17.044ns
   Maximum output required time after clock: 10.231ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_100mhz'
  Clock period: 21.580ns (frequency: 46.340MHz)
  Total number of paths / destination ports: 95225787920 / 3343
-------------------------------------------------------------------------
Delay:               21.580ns (Levels of Logic = 17)
  Source:            openmips/id_ex/ex_aluop_2 (FF)
  Destination:       openmips/pc_reg/pc_24 (FF)
  Source Clock:      clk_100mhz rising
  Destination Clock: clk_100mhz rising

  Data Path: openmips/id_ex/ex_aluop_2 to openmips/pc_reg/pc_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            14   0.447   0.958  openmips/id_ex/ex_aluop_2 (openmips/id_ex/ex_aluop_2)
     LUT4:I3->O            3   0.205   0.755  openmips/ex/aluop_i[7]_aluop_i[7]_OR_473_o694_SW0 (N222)
     LUT6:I4->O           18   0.203   1.050  openmips/ex/aluop_i[7]_aluop_i[7]_OR_473_o694_1 (openmips/ex/aluop_i[7]_aluop_i[7]_OR_473_o694)
     LUT4:I3->O            2   0.205   0.616  openmips/ex/Mmux_opdata1_mult110 (openmips/ex/opdata1_mult<0>)
     DSP48A1:A0->P47      18   4.560   1.049  openmips/ex/Mmult_hilo_temp (openmips/ex/Mmult_hilo_temp_P47_to_Mmult_hilo_temp1)
     DSP48A1:C30->PCOUT47    1   2.689   0.000  openmips/ex/Mmult_hilo_temp1 (openmips/ex/Mmult_hilo_temp1_PCOUT_to_Mmult_hilo_temp2_PCIN_47)
     DSP48A1:PCIN47->P0    5   2.264   0.714  openmips/ex/Mmult_hilo_temp2 (openmips/ex/hilo_temp<17>)
     INV:I->O              1   0.206   0.000  openmips/ex/n0547<17>1_INV_0 (openmips/ex/n0547<17>)
     MUXCY:S->O            1   0.172   0.000  openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<17> (openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<17>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<18> (openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<18>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<19> (openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<19>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<20> (openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_cy<20>)
     XORCY:CI->O           4   0.180   0.684  openmips/ex/Madd_hilo_temp[63]_GND_10_o_add_155_OUT_xor<21> (openmips/ex/hilo_temp[63]_GND_10_o_add_155_OUT<21>)
     LUT6:I5->O            4   0.205   1.048  openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT1373 (openmips/id_reg1_o<21>)
     LUT6:I0->O            1   0.203   0.580  openmips/id/Mmux_branch_target_address_o1012 (openmips/id/Mmux_branch_target_address_o1012)
     LUT6:I5->O            4   0.205   0.684  openmips/id/Mmux_branch_target_address_o1017 (openmips/id/Mmux_branch_target_address_o1017)
     LUT6:I5->O           17   0.205   1.132  openmips/id/Mmux_next_inst_in_delayslot_o11 (openmips/branch_flag)
     LUT6:I4->O            1   0.203   0.000  openmips/pc_reg/Mmux_pc[31]_branch_target_address_i[31]_mux_7_OUT1 (openmips/pc_reg/pc[31]_branch_target_address_i[31]_mux_7_OUT<0>)
     FDRE:D                    0.102          openmips/pc_reg/pc_0
    ----------------------------------------
    Total                     21.580ns (12.311ns logic, 9.269ns route)
                                       (57.0% logic, 43.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_100mhz'
  Total number of paths / destination ports: 416672 / 2588
-------------------------------------------------------------------------
Offset:              17.044ns (Levels of Logic = 14)
  Source:            sw<7> (PAD)
  Destination:       openmips/pc_reg/pc_24 (FF)
  Destination Clock: clk_100mhz rising

  Data Path: sw<7> to openmips/pc_reg/pc_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          2487   1.222   2.668  sw_7_IBUF (openmips/id_ex/Reset_OR_DriverANDClockEnable)
     LUT2:I0->O          257   0.203   2.431  openmips/id/Mmux_reg1_addr_o21 (openmips/reg1_addr<1>)
     LUT6:I0->O            1   0.203   0.827  openmips/regfile/Mmux_raddr1[4]_regs[31][31]_wide_mux_46_OUT_867 (openmips/regfile/Mmux_raddr1[4]_regs[31][31]_wide_mux_46_OUT_867)
     LUT6:I2->O            1   0.203   0.000  openmips/regfile/Mmux_raddr1[4]_regs[31][31]_wide_mux_46_OUT_322 (openmips/regfile/Mmux_raddr1[4]_regs[31][31]_wide_mux_46_OUT_322)
     MUXF7:I1->O           1   0.140   0.808  openmips/regfile/Mmux_raddr1[4]_regs[31][31]_wide_mux_46_OUT_2_f7_21 (openmips/regfile/raddr1[4]_regs[31][31]_wide_mux_46_OUT<2>)
     LUT6:I3->O            1   0.205   0.580  openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT1551 (openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT155)
     LUT6:I5->O            1   0.205   0.827  openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT1552 (openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT1551)
     LUT5:I1->O            6   0.203   0.992  openmips/id/Mmux_GND_6_o_imm[31]_mux_225_OUT1553 (openmips/id_reg1_o<2>)
     LUT6:I2->O            1   0.203   0.580  openmips/id/Mmux_branch_target_address_o1014_SW0 (N479)
     LUT6:I5->O            1   0.205   0.924  openmips/id/Mmux_branch_target_address_o1015 (openmips/id/Mmux_branch_target_address_o1015)
     LUT6:I1->O            1   0.203   0.684  openmips/id/Mmux_branch_target_address_o1016 (openmips/id/Mmux_branch_target_address_o1016)
     LUT6:I4->O            4   0.203   0.684  openmips/id/Mmux_branch_target_address_o1017 (openmips/id/Mmux_branch_target_address_o1017)
     LUT6:I5->O           17   0.205   1.132  openmips/id/Mmux_next_inst_in_delayslot_o11 (openmips/branch_flag)
     LUT6:I4->O            1   0.203   0.000  openmips/pc_reg/Mmux_pc[31]_branch_target_address_i[31]_mux_7_OUT1 (openmips/pc_reg/pc[31]_branch_target_address_i[31]_mux_7_OUT<0>)
     FDRE:D                    0.102          openmips/pc_reg/pc_0
    ----------------------------------------
    Total                     17.044ns (3.908ns logic, 13.136ns route)
                                       (22.9% logic, 77.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sw<7>'
  Total number of paths / destination ports: 3597 / 64
-------------------------------------------------------------------------
Offset:              7.756ns (Levels of Logic = 68)
  Source:            sw<7> (PAD)
  Destination:       openmips/ex/hilo_temp1_63 (LATCH)
  Destination Clock: sw<7> rising

  Data Path: sw<7> to openmips/ex/hilo_temp1_63
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          2487   1.222   2.928  sw_7_IBUF (openmips/id_ex/Reset_OR_DriverANDClockEnable)
     LUT6:I0->O            2   0.203   0.617  openmips/ex/Mmux_HI1102 (openmips/ex/LO<0>)
     LUT2:I1->O            1   0.205   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_lut<0> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_lut<0>)
     MUXCY:S->O            1   0.172   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<0> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<0>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<1> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<1>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<2> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<2>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<3> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<3>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<4> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<4>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<5> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<5>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<6> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<6>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<7> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<7>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<8> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<8>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<9> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<9>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<10> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<10>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<11> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<11>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<12> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<12>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<13> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<13>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<14> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<14>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<15> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<15>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<16> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<16>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<17> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<17>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<18> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<18>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<19> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<19>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<20> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<20>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<21> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<21>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<22> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<22>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<23> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<23>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<24> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<24>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<25> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<25>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<26> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<26>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<27> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<27>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<28> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<28>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<29> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<29>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<30> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<30>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<31> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<31>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<32> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<32>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<33> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<33>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<34> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<34>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<35> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<35>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<36> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<36>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<37> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<37>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<38> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<38>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<39> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<39>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<40> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<40>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<41> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<41>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<42> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<42>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<43> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<43>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<44> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<44>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<45> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<45>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<46> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<46>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<47> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<47>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<48> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<48>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<49> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<49>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<50> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<50>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<51> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<51>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<52> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<52>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<53> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<53>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<54> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<54>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<55> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<55>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<56> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<56>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<57> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<57>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<58> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<58>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<59> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<59>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<60> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<60>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<61> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<61>)
     MUXCY:CI->O           0   0.019   0.000  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<62> (openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_cy<62>)
     XORCY:CI->O           1   0.180   0.808  openmips/ex/Madd_hilo_temp_i[63]_HI[31]_add_162_OUT_xor<63> (openmips/ex/hilo_temp_i[63]_HI[31]_add_162_OUT<63>)
     LUT3:I0->O            1   0.205   0.000  openmips/ex/Mmux_aluop_i[7]_hilo_temp1[63]_select_187_OUT601 (openmips/ex/aluop_i[7]_hilo_temp1[63]_select_187_OUT<63>)
     LDE_1:D                   0.037          openmips/ex/hilo_temp1_63
    ----------------------------------------
    Total                      7.756ns (3.402ns logic, 4.354ns route)
                                       (43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'openmips/ex/_n0586'
  Total number of paths / destination ports: 2210 / 130
-------------------------------------------------------------------------
Offset:              6.807ns (Levels of Logic = 67)
  Source:            sw<7> (PAD)
  Destination:       openmips/ex/hilo_temp_o_63 (LATCH)
  Destination Clock: openmips/ex/_n0586 falling

  Data Path: sw<7> to openmips/ex/hilo_temp_o_63
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          2487   1.222   2.928  sw_7_IBUF (openmips/id_ex/Reset_OR_DriverANDClockEnable)
     LUT6:I0->O            1   0.203   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_lut<0> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_lut<0>)
     MUXCY:S->O            1   0.172   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<0> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<0>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<1> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<1>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<2> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<2>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<3> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<3>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<4> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<4>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<5> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<5>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<6> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<6>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<7> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<7>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<8> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<8>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<9> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<9>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<10> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<10>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<11> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<11>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<12> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<12>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<13> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<13>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<14> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<14>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<15> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<15>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<16> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<16>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<17> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<17>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<18> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<18>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<19> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<19>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<20> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<20>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<21> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<21>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<22> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<22>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<23> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<23>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<24> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<24>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<25> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<25>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<26> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<26>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<27> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<27>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<28> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<28>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<29> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<29>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<30> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<30>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<31> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<31>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<32> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<32>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<33> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<33>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<34> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<34>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<35> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<35>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<36> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<36>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<37> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<37>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<38> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<38>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<39> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<39>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<40> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<40>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<41> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<41>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<42> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<42>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<43> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<43>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<44> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<44>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<45> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<45>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<46> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<46>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<47> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<47>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<48> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<48>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<49> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<49>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<50> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<50>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<51> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<51>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<52> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<52>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<53> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<53>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<54> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<54>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<55> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<55>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<56> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<56>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<57> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<57>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<58> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<58>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<59> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<59>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<60> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<60>)
     MUXCY:CI->O           1   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<61> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<61>)
     MUXCY:CI->O           0   0.019   0.000  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<62> (openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_cy<62>)
     XORCY:CI->O           1   0.180   0.684  openmips/ex/Madd_mulres[63]_GND_10_o_add_171_OUT_xor<63> (openmips/ex/mulres[63]_GND_10_o_add_171_OUT<63>)
     LUT6:I4->O            1   0.203   0.000  openmips/ex/aluop_i[7]_hilo_temp_o[63]_select_185_OUT<63>1 (openmips/ex/aluop_i[7]_hilo_temp_o[63]_select_185_OUT<63>)
     LDC:D                     0.037          openmips/ex/hilo_temp_o_63
    ----------------------------------------
    Total                      6.807ns (3.195ns logic, 3.612ns route)
                                       (46.9% logic, 53.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_100mhz'
  Total number of paths / destination ports: 3381 / 19
-------------------------------------------------------------------------
Offset:              10.231ns (Levels of Logic = 8)
  Source:            openmips/pc_reg/pc_5 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      clk_100mhz rising

  Data Path: openmips/pc_reg/pc_5 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            49   0.447   1.878  openmips/pc_reg/pc_5 (openmips/pc_reg/pc_5)
     begin scope: 'inst_rom:a<3>'
     LUT6:I1->O            1   0.203   0.924  U0/xst_options.dist_mem_inst/gen_rom.rom_inst/Mram_spo_int84113 (U0/xst_options.dist_mem_inst/gen_rom.rom_inst/Mram_spo_int84112)
     LUT6:I1->O            1   0.203   0.808  U0/xst_options.dist_mem_inst/gen_rom.rom_inst/Mram_spo_int84115 (U0/xst_options.dist_mem_inst/gen_rom.rom_inst/Mram_spo_int84114)
     LUT3:I0->O            2   0.205   0.845  U0/xst_options.dist_mem_inst/gen_rom.rom_inst/Mram_spo_int84116 (spo<29>)
     end scope: 'inst_rom:spo<29>'
     LUT6:I3->O            1   0.205   0.000  mux8t1_4/Mmux_o_31 (mux8t1_4/Mmux_o_31)
     MUXF7:I1->O           7   0.140   1.021  mux8t1_4/Mmux_o_2_f7_0 (digit<1>)
     LUT4:I0->O            1   0.203   0.579  decoder_7seg/Mram_segment11 (seg_0_OBUF)
     OBUF:I->O                 2.571          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                     10.231ns (4.177ns logic, 6.054ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk_100mhz
------------------+---------+---------+---------+---------+
                  | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock      |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------+---------+---------+---------+---------+
clk_100mhz        |   21.580|         |         |         |
openmips/ex/_n0586|         |    4.082|         |         |
sw<7>             |    4.600|         |         |         |
------------------+---------+---------+---------+---------+

Clock to Setup on destination clock openmips/ex/_n0586
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_100mhz     |         |         |   22.725|         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock sw<7>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_100mhz     |    6.551|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 29.00 secs
Total CPU time to Xst completion: 29.50 secs
 
--> 

Total memory usage is 256936 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  230 (   0 filtered)
Number of infos    :    7 (   0 filtered)