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HDL Examples

AXI_IP Examples

Topic Description
How to use AXI Complex Multiplier This example shows how to use Complex Multiplier
How to use AXI DDS Compiler This example shows how to use DDS Compiler
How to use AXI Fast Fourier Transform This example shows how to use Fast Fourier Transform by performing FFT and IFFT.

Digital Communications Examples

Topic Description
16-QAM demodulator This design implements an equalized 16-QAM demodulator for use in a software defined radio.
Costas loop carrier recovery This design implements the Costas loop using the DDS block.

Digital Filtering Examples

Topic Description
High speed SSR FIR This reference design can be used as a starting design point when efficient implementations of very high data rate (over 1 Gsps) Single Rate FIRs are required.
2nd-order Direct Form I implementation This design example shows two distinct FPGA implementations of a 2nd order IIR filter in Direct Form I, and compares them to the double precision Simulink IIR filter block.
LMS based adaptive equalization This design shows a T/2 adaptive Fractionally Space Equalizer (FSE) operating on a 16-QAM data source with noise and filtering introduced in the channel model.
LMS-based adaptive equalization (Synthesizable RTL) This design shows how to use the MCode block to create fully synthesizable register transfer level (RTL) designs in Model Composer.
Multi-channel, folded implementation This design demonstrates how multiple IIR filters can be implemented using a single time-shared second-order section (biquad). Specifically, 15 distinct IIR filters, each consisting of four cascaded biquads, are realized in a "folded" architecture that uses a single hardware biquad.
Reloadable FIR Filter This example shows how to reload the 5-tap symmetric FIR with the coefficient values of 7 8 9 8 7.

Floating Point Examples

Topic Description
2nd-order Direct Form II implementation This design shows two distinct FPGA implementations of a 2nd order IIR filter in Direct Form II, and compares them to the double precision Simulink IIR filter block.
3x3 Matrix Determinant This design demonstrates the calculation of the determinant of a 3x3 matrix with real, single precision floating point elements. It showcases the Black Box block for bringing hand-coded VHDL or Verilog code into Model Composer. It also shows the DSPFP32 for performing floating-point operations on Versal devices.

General Examples

Topic Description
Color space converter This design implements R-G-B to Y-Pr-Pb color space conversion.
2D DWT filter This design performs a 2D DWT filtering on 64x64 pixel image.
Two Dimensional FFT using Corner Turning Technique for MRI Sagittal Image Reconstruction This design performs a two dimensional FFT (2D-FFT) on MRI input data.

MATH Examples

Topic Description
Logic and Cores Fibonacci Number Generator This design is a logic and cores implementation of a Fibonacci number generator. That is, given a non-negative integer n, it computes the recursively defined sequence x_0 = 1, x_1 = 1, ... , x_n = x_{n-2} + x_{n-1}.
MCode-Based Fibonacci Number Generator This design implements a Fibonacci number generator in an MCode block. That is, given a non-negative integer n, it computes the recursively defined sequence x_0 = 1, x_1 = 1, ... , n_n = x_{n-2} + x_{n-1}.

RFSoC Examples

Topic Description
Programmatic Digital Down converter using SSR This design implements a digital down converter that reduces the sampling rate of the input signal to match the desired output sampling rate. In this example we go from 1.5GSPS to 187.5MSPS.
IFFT computation using the Vector FFT block This model computes the Inverse FFT using an FFT block.
Highly Optimized Symmetric Interpolation FIR implementation This design shows a 273-tap polyphase FIR filter, which consumes 4 samples per clock cycle, interpolate by 2 (1 GSPS input rate to 2GSPS output rate), and Symmetric coefficients using FIR compiler blocks.

Copyright 2021 Xilinx

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.