DisplayPort not wokring with standalone driver ，the clock cannot be configured successfully in in Vitis Unified IDE 2024.1

[Bethexone]

Zynq UltraScale+ MPSoC 3eg , When I run xdpdma_video_example in Vitis Unified IDE 2024.1，The clock configuration could not be successful ，It is Unable to proceed with debugging Nor can it continue to run。
PAUSED ON CANNOT RESUME. CANNOT READ REGISTER 'PC'. CANNOT READ REGISTER 'R0'. CORTEX-A53 #0: EDITR NOT READY

DPDMA Generic Video Example Test 
Generating Overlay.....

HPD event .......... 
! Connected.

Lane count =	2

Link rate =	20



Starting Training...

	! Training succeeded.

AVBuf Input Ref Clk = 3333333333 Hz
AVBuf Input Ref Clk = 3333333333 Hz

In the wrong place,inxavbuf_clk.c: 480, i.e. the instance of PllInstancePtr passed in when running XAVBuf_ConfigurePll
Flag = XAVBuf_ConfigurePll(&PllInstancePtr);

cam_wrapper.zip

embeddedsw/XilinxProcessorIPLib/drivers/dpdma/examples/xdppsu_interrupt.c

Line 302 in 3728f54

XAVBuf_SetPixelClock(RunCfgPtr->PixClkHz);

[Bethexone]

I found my mistake, the DisplayPort clock selection in the zynq IP core is wrong, it should be selected as follows