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Interfacing with the PL #1105
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By looking up the AIETargetModel it seems to be that there is what is called ShimPL tiles that are mutually exclusive to ShimDMA tiles in the shim row. However, having 16 ShimDMA tiles means that we are only left with 34 ShimPL tiles, whereas in AM009, it states that there 39 PL interface tiles. This is also visible on Vitis analyzer for a large enough design by experience. How is that possible? |
It's possible to query vivado for the exact information. To my knowledge this is the only place the valid sites are documented.
In particular, note that at the very ends of the device, the NOC exists and can be used, even though there is not PL below the AIE tile |
Thanks @stephenneuendorffer! That was the most accurate way to figure it out. (I believe there is a typo in the last line of your commands where it should have been AIE_NOC instead of AIE_PL, right?) Looking at the results
As I have known before, on the AIE1 xcvc1902 device, we have 39 adjacent PL interface tiles centred in the shim row from 6 to 44, whereas the NOC/DMA tiles are the same as mentioned in tutorial 5. That brings a point: ShimPL and ShimDMA tiles are NOT placed in a mutually exclusive manner as given in the AIETargetModel of the xcvc1902. I believe that should be fixed. Otherwise, MLIR-AIE would not work properly when the PL is in the game, right? |
Yes the model is incorrect here... Care to make a patch? Note that in shim tiles that include both a PL interface and a NOC interface, they are somewhat mutually exclusive since they share the stream interconnect. Both cannot be used with full bandwidth. Would love to see people using the PL interface more! |
Yup, fixed! |
Maybe this is helpful #1623 and passthrough_dmas_plio |
Following the tutorials, it is only clear how to interface with the DDR directly through the ShimDMA in tutorial 5, i.e. from L1 directly to L3. What about interfacing with the PL using the PLIOs (to enable L2 or do some calculations while streaming)? Tutorial 5 only states that
So is it exactly the same way with the 39 PL Interface tiles? If yes, what are the shim tiles that have the PL Interface tiles? And how to precise the data width carried by a PLIO as we do with the ADF API?
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