[LLVM][XTHeadVector] Implement intrinsics for vsmul. (llvm#75)

* [NFC][XTHeadVector] Update README.

* [LLVM][XTHeadVector] Add test cases.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Implement intrinsics for vsmul.

Author: zhanyi22333

README.md

@@ -52,6 +52,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `12.12. Vector Single-Width Integer Multiply-Add Instructions`
     - (Done) `12.13. Vector Widening Integer Multiply-Add Instructions`
     - (Done) `12.14. Vector Integer Merge and Move Instructions`
+    - (Done) `13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -793,4 +793,8 @@ let TargetPrefix = "riscv" in {
     let ScalarOperand = 1;
     let VLOperand = 2;
   }
+
+  // 13.3.  Vector Single-Width Fractional Multiply with Rounding and Saturation Instructions
+  defm th_vsmul : XVBinaryABX;
+
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2089,6 +2089,21 @@ multiclass XVPseudoVWMAC_VX {
   }
 }
 
+multiclass XVPseudoVSMUL_VV_VX {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVSIMulV_MX = !cast<SchedWrite>("WriteVSMulV_" # mx);
+    defvar WriteVSIMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
+    defvar ReadVSIMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
+    defvar ReadVSIMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
+
+    defm "" : XVPseudoBinaryV_VV<m>,
+              Sched<[WriteVSIMulV_MX, ReadVSIMulV_MX, ReadVSIMulV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VX<m>,
+              Sched<[WriteVSIMulX_MX, ReadVSIMulV_MX, ReadVSIMulX_MX, ReadVMask]>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -3020,4 +3035,18 @@ let Predicates = [HasVendorXTHeadV] in {
   }
 } // Predicates = [HasVendorXTHeadV]
 
-include "RISCVInstrInfoXTHeadVVLPatterns.td"
+//===----------------------------------------------------------------------===//
+// 13.3. Vector Single-Width Fractional Multiply with Rounding and
+// Saturation Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VSMUL  : XVPseudoVSMUL_VV_VX;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vsmul", "PseudoTH_VSMUL", AllIntegerXVectors>;
+  // defm : XVPatBinaryV_VV_VX<"int_riscv_th_vsmul", "PseudoTH_VSMUL", AllIntegerXVectors, isSEWAware=1>;
+} // Predicates = [HasVendorXTHeadV]
+
+include "RISCVInstrInfoXTHeadVVLPatterns.td"