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controller.qsf
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controller.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 19:09:09 September 08, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# controller_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY controller
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:09:09 SEPTEMBER 08, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
# SW0 - SW7
set_location_assignment PIN_N25 -to input[0]
set_location_assignment PIN_N26 -to input[1]
set_location_assignment PIN_P25 -to input[2]
set_location_assignment PIN_AE14 -to input[3]
set_location_assignment PIN_AF14 -to input[4]
set_location_assignment PIN_AD13 -to input[5]
set_location_assignment PIN_AC13 -to input[6]
set_location_assignment PIN_C13 -to input[7]
# SW15 - SW17
set_location_assignment PIN_G26 -to input_ready
set_location_assignment PIN_N23 -to reset
# LEDR0 - LEDR7
set_location_assignment PIN_AE23 -to output[0]
set_location_assignment PIN_AF23 -to output[1]
set_location_assignment PIN_AB21 -to output[2]
set_location_assignment PIN_AC22 -to output[3]
set_location_assignment PIN_AD22 -to output[4]
set_location_assignment PIN_AD23 -to output[5]
set_location_assignment PIN_AD21 -to output[6]
set_location_assignment PIN_AC21 -to output[7]
# LEDG0 - LEDG7
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC ON
set_global_assignment -name RTLV_GROUP_RELATED_NODES ON
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_N2 -to clock_board
set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF
set_location_assignment PIN_AC23 -to cs
set_location_assignment PIN_Y21 -to mosi
set_location_assignment PIN_AD24 -to miso
set_location_assignment PIN_AD25 -to sclk
set_location_assignment PIN_U18 -to state_cu[0]
set_location_assignment PIN_V18 -to state_cu[1]
set_location_assignment PIN_W19 -to state_cu[2]
set_location_assignment PIN_AF22 -to state_cu[3]
set_location_assignment PIN_AE22 -to state_cu[4]
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS ON
set_global_assignment -name VHDL_FILE vhdl/library/arch.vhd
set_global_assignment -name VHDL_FILE vhdl/library/util.vhd
set_global_assignment -name VHDL_FILE vhdl/components/01_control_unit/control_unit.vhd
set_global_assignment -name VHDL_FILE vhdl/components/02_program_counter/program_counter.vhd
set_global_assignment -name VHDL_FILE vhdl/components/03_arithmetic_logic_unit/arithmetic_logic_unit.vhd
set_global_assignment -name VHDL_FILE vhdl/components/04_instruction_register/instruction_register.vhd
set_global_assignment -name VHDL_FILE vhdl/components/05_memory/memory.vhd
set_global_assignment -name VHDL_FILE vhdl/components/06_accumulator/accumulator.vhd
set_global_assignment -name VHDL_FILE vhdl/components/07_controller/controller.vhd
set_global_assignment -name VHDL_FILE vhdl/components/08_loader/sd_controller.vhd
set_global_assignment -name VHDL_FILE vhdl/components/08_loader/loader.vhd
set_global_assignment -name VHDL_FILE vhdl/components/08_loader/dummy_loader.vhd
set_global_assignment -name VHDL_FILE vhdl/tests/entity_tests/ap004/program_counter.vhd
set_global_assignment -name VHDL_FILE vhdl/tests/entity_tests/ap008/instruction_register.vhd
set_global_assignment -name VHDL_FILE vhdl/tests/entity_tests/ap006/arithmetic_logic_unit.vhd
set_global_assignment -name VHDL_FILE vhdl/tests/entity_tests/ap010/accumulator.vhd
set_global_assignment -name CDF_FILE cdf/flash.cdf
set_global_assignment -name VECTOR_WAVEFORM_FILE "vwf/test001-controller.vwf"
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/Bueddl/Documents/Altera/hc1-mikrocontroller/vwf/test001-controller.vwf"
set_location_assignment PIN_AC14 -to ld_addr[0]
set_location_assignment PIN_AD15 -to ld_addr[1]
set_location_assignment PIN_AE15 -to ld_addr[2]
set_location_assignment PIN_AF13 -to ld_addr[3]
set_location_assignment PIN_AE13 -to ld_addr[4]
set_location_assignment PIN_AE12 -to ld_addr[5]
set_location_assignment PIN_AD12 -to ld_addr[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top