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sdiodrv.c
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: sw/sdiodrv.c
// {{{
// Project: SD-Card controller
//
// Purpose: This is the software driver for the SDIO controller, used for
// interacting with an SD Card in SDIO (4b) mode.
//
// Entry points: This driver has four external entry points, which can be used
// to define it's operation:
//
// 1. sdio_init
// This should be called first. It will generate the driver's
// data structure, and attempt to interact with the card.
// It needs to be passed the hardware address of the device in
// the address map.
// 2. sdio_write(dev, sector, count, buf)
// Writes "count" sectors of data to the device, starting at
// the sector numbered "sector". The data are sourced from the
// *buf pointer, which *must* either be word aligned or the CPU
// must be able to handle unaligned accesses.
//
// If SDMULTI is set, the write multiple blocks command will be
// used for better performance. SDMULTI *must* be set in order to
// use the DMA.
//
// 3. sdio_read(dev, sector, count, buf)
// Reads "count" sectors of data to the device, starting at
// the sector numbered "sector". The data are saved into the
// *buf pointer, which *must* either be word aligned or the CPU
// must be able to handle unaligned accesses.
//
// If SDMULTI is set, the read multiple blocks command will be
// used for better performance. This requires that the clock
// shutdown bit be set, to avoid losing data. As with writing,
// SDMULTI must be set in order to use the DMA.
//
// 4. sdio_ioctl
//
// Issues:
// - This controller only handles 3.3V mode. Even if hardware exists for
// switching to 1.8V, this driver doesn't (yet) enable it.
// - The controller doesn't really recover well from a failed init.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2016-2025, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
#include <stdlib.h>
#include <stdint.h>
typedef uint8_t BYTE;
typedef uint16_t WORD;
typedef uint32_t DWORD, LBA_t, UINT;
#include <diskio.h>
#include "sdiodrv.h"
// tx* -- debugging output functions
// {{{
// Debugging isn't quite as simple as using printf(), since I want to guarantee
// that I can still compile and build this into a memory that isn't large enough
// to hold a printf function. The txstr(), txchr(), and txhex() functions fit
// that low memory footprint need. For cases where these are not sufficient,
// we use the STDIO_DEBUG flag to determine if the regular ?rintf() functions
// are available.
#ifndef TXFNS_H
#include <stdio.h>
#define txchr(A) putchar(A)
#define txstr(A) fputs(A, stdout)
#define txhex(A) printf("%08x", A)
#define txdecimal(A) printf("%d", A)
#define STDIO_DEBUG
#else
// extern void txstr(const char *);
// extern void txhex(unsigned);
// extern void txdecimal(int);
#define printf(...)
#endif
// }}}
// WBScope
// {{{
// The following defines may be useful when a WBScope has been attached
// to the device. They are mostly useful for debugging. If no WBScope
// is attached, these macros are given null definitions.
#ifdef _BOARD_HAS_SDIOSCOPE
#define SET_SCOPE _sdioscope->s_ctrl = 0x04000100
#define TRIGGER_SCOPE _sdioscope->s_ctrl = 0xff000100
#else
#define SET_SCOPE
#define TRIGGER_SCOPE
#endif
// }}}
// SDINFO & SDDEBUG
// {{{
// These are designed to be compile time constants, to allow the compiler to
// remove the logic they generate for space reasons.
// SDDEBUG: Set to turn on debugging output. Ideally, debugging output
// should not be necessary in a *working* design, so its use is
// primary until the design starts working. This debugging
// output will tell you (among other things) when the design
// issues commands, what command are issued, which routines are
// called. etc.
// SDINFO: Set to turns on a verbose reporting. This will dump values of
// registers, together with their meanings. When reading,
// it will dump sectors read. Often requires SDDEBUG.
static const int SDINFO = 0, SDDEBUG = 0;
// }}}
// Compile time DMA controls
// {{{
// OPT_SDIODMA will be defined if the design was built in an environment that
// (may have potentially) had a hardware DMA built into it. (We'll still
// check.) If not, SDEXTDMA controls whether or not calls to an _external_
// DMA should be generated. These would be calls to the ZipCPU's DMA. To
// avoid all external DMA calls, simply set SDEXTDMA to zero.
#ifdef OPT_SDIODMA
static const int SDEXTDMA=0;
#else
static const int SDEXTDMA=1;
#endif
// }}}
// SDMULTI
// {{{
// SDMULTI: Controls whether the read multiple block or write multiple block
// commands will be used. Set to 1 to use these commands, 0 otherwise.
// SDMULTI *must* be set to use the internal DMA, otherwise only block level
// commands will be issued.
static const int SDMULTI = 1;
// }}}
// }}}
#define NEW_MUTEX
#define GRAB_MUTEX
#define RELEASE_MUTEX
#ifndef CLEAR_DCACHE
#define CLEAR_DCACHE
#endif
typedef struct SDIODRV_S {
SDIO *d_dev;
uint32_t d_CID[4], d_OCR;
char d_SCR[8], d_CSD[16];
uint16_t d_RCA;
uint32_t d_sector_count, d_block_size;
} SDIODRV;
static const uint32_t
// Command bit enumerations
SDIO_NULLCMD = 0x00000080,
SDIO_RNONE = 0x00000000,
SDIO_R1 = 0x00000100,
SDIO_R2 = 0x00000200,
SDIO_R1b = 0x00000300,
SDIO_WRITE = 0x00000400,
SDIO_MEM = 0x00000800,
SDIO_FIFO = 0x00001000,
SDIO_DMA = 0x00002000,
SDIO_CMDBUSY = 0x00004000,
SDIO_ERR = 0x00008000,
SDIO_CMDTMOUT = 0x00000000,
SDIO_CMDEOKAY = 0x00010000,
SDIO_CMDCRCER = 0x00020000,
SDIO_CMDFRMER = 0x00030000,
SDIO_CMDECODE = 0x00030000,
SDIO_REMOVED = 0x00040000,
SDIO_PRESENTN = 0x00080000,
SDIO_CARDBUSY = 0x00100000,
SDIO_BUSY = (SDIO_CARDBUSY|SDIO_CMDBUSY|SDIO_DMA|SDIO_MEM),
SDIO_CMDERR = 0x00200000,
SDIO_RXERR = 0x00400000, // RX Error present
SDIO_RXECODE = 0x00800000, // RX Error code
SDIO_DMAERR = 0x01000000,
SDIO_HWRESET = 0x02000000,
SDIO_ACK = 0x04000000, // Expect a CRC ACK token
SDIO_RESET = 0x52000000,
// PHY enumerations
SDPHY_DDR = 0x00004100, // Requires CK90
SDPHY_DS = 0x00004300, // Requires DDR & CK90
SDPHY_W1 = 0x00000000,
SDPHY_W4 = 0x00000400,
SDPHY_W8 = 0x00000800,
SDPHY_WBEST = 0x00000c00,
SDPHY_PPDAT = 0x00001000, // Push pull drive for data
SDPHY_PPCMD = 0x00002000, // Push pull drive for cmd wire
SDPHY_PUSHPULL = SDPHY_PPDAT | SDPHY_PPCMD,
SDIOCK_CK90 = 0x00004000,
SDIOCK_SHUTDN = 0x00008000,
SDPHY_PHASEMSK= 0x001f0000,
// IO clock speeds
SDIOCK_100KHZ = 0x000000fc,
SDIOCK_200KHZ = 0x0000007f,
SDIOCK_400KHZ = 0x00000041,
SDIOCK_1MHZ = 0x0000001b,
SDIOCK_5MHZ = 0x00000007,
SDIOCK_12MHZ = 0x00000004,
SDIOCK_25MHZ = 0x00000003,
SDIOCK_50MHZ = 0x00000002,
SDIOCK_100MHZ = 0x00000001,
SDIOCK_200MHZ = 0x00000000,
SDIOCK_MASK = 0x000000ff,
SDPHY_1P8V = 0x00400000,
SDPHY_1P8VSPT = 0x00800000, // 1.8v is supported
SDIOCK_DS = SDIOCK_25MHZ | SDPHY_W4 | SDPHY_PUSHPULL,
SDIOCK_HS = SDIOCK_50MHZ | SDPHY_W4 | SDPHY_PUSHPULL,
// Speed abbreviations
SDIOCK_SDR12 = SDIOCK_DS | SDPHY_1P8V,
SDIOCK_SDR25 = SDIOCK_HS | SDPHY_1P8V,
SDIOCK_DDR50 = SDIOCK_50MHZ | SDPHY_W4 | SDPHY_PUSHPULL | SDPHY_DDR | SDPHY_1P8V,
SDIOCK_SDR50 = SDIOCK_100MHZ | SDPHY_W4 | SDPHY_PUSHPULL | SDPHY_1P8V,
SDIOCK_SDR104 = SDIOCK_200MHZ | SDPHY_W4 | SDPHY_PUSHPULL | SDPHY_1P8V,
//
SPEED_SLOW = SDIOCK_400KHZ,
SPEED_DEFAULT= SDIOCK_DS,
SPEED_FAST = SDIOCK_HS,
//
SECTOR_16B = 0x04000000,
SECTOR_64B = 0x06000000,
SECTOR_512B = 0x09000000,
SECTOR_MASK = 0x0f000000,
//
SDIO_CMD = 0x00000040,
SDIO_READREG = SDIO_CMD | SDIO_R1,
SDIO_READREGb = SDIO_CMD | SDIO_R1b,
SDIO_READR2 = (SDIO_CMD | SDIO_R2),
SDIO_WRITEBLK = (SDIO_CMD | SDIO_R1b | SDIO_ERR
| SDIO_ACK
| SDIO_WRITE | SDIO_MEM) + 24,
SDIO_WRMULTI = (SDIO_CMD | SDIO_R1b
| SDIO_ACK
| SDIO_WRITE | SDIO_MEM) + 25,
SDIO_WRDMA = SDIO_WRMULTI | SDIO_DMA,
SDIO_READBLK = (SDIO_CMD | SDIO_R1
| SDIO_MEM) + 17,
SDIO_RDMULTI = (SDIO_CMD | SDIO_R1
| SDIO_MEM) + 18,
SDIO_READDMA = SDIO_RDMULTI | SDIO_DMA,
SDIO_R1ERR = 0xff800000,
S18R = (1<<24),
XPC = (1<<28);
static void sdio_wait_while_busy(SDIODRV *dev);
static void sdio_go_idle(SDIODRV *dev);
static void sdio_all_send_cid(SDIODRV *dev);
static void sdio_dump_cid(SDIODRV *dev);
static uint32_t sdio_send_rca(SDIODRV *dev);
static void sdio_select_card(SDIODRV *dev); // CMD7
static void sdio_unselect_card(SDIODRV *dev); // CMD7
static uint32_t sdio_send_if_cond(SDIODRV *dev, uint32_t ifcond); // CMD8
static uint32_t sdio_send_op_cond(SDIODRV *dev, uint32_t opcond); // ACMD41
static void sdio_send_voltage_switch(SDIODRV *dev); // CMD11
static void sdio_send_tuning_block(SDIODRV *dev); // CMD19
static void sdio_set_bus_width(SDIODRV *dev, uint32_t width); // ACMD6
static void sdio_send_app_cmd(SDIODRV *dev); // CMD 55
static uint32_t sdio_read_ocr(SDIODRV *dev, uint32_t width); // CMD 58
static void sdio_decode_cmd(const uint32_t cmd);
static void sdio_dump_err(unsigned);
static void sdio_dump_scr(SDIODRV *dev);
static void sdio_dump_ocr(SDIODRV *dev);
static unsigned sdio_get_r1(SDIODRV *dev);
static void sdio_dump_r1(unsigned);
static int sdio_write_block(SDIODRV *dev, uint32_t sector, uint32_t *buf); // CMD 24
static int sdio_read_block(SDIODRV *dev, uint32_t sector, uint32_t *buf); // CMD 17
extern SDIODRV *sdio_init(SDIO *dev);
extern int sdio_write(SDIODRV *dev, const unsigned sector, const unsigned count, const char *buf);
extern int sdio_read(SDIODRV *dev, const unsigned sector, const unsigned count, char *buf);
extern int sdio_ioctl(SDIODRV *dev, char cmd, char *buf);
void sdio_wait_while_busy(SDIODRV *dev) {
// {{{
// Could also do a system call and yield to the scheduler while waiting
// if (SDIO_OS) {
// os_wait(dev->d_int);
// } else if (SDIO_INT) {
// // Can wait for an interrupt here, such as by calling an
// // external wait_int function with our interrupt ID.
// wait_int(dev->d_int);
// } else {
// Busy wait implementation
uint32_t st;
st = dev->d_dev->sd_cmd;
while(st & SDIO_BUSY)
st = dev->d_dev->sd_cmd;
// }
}
// }}}
void sdio_go_idle(SDIODRV *dev) { // CMD0
// {{{
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = SDIO_REMOVED | SDIO_CMD | SDIO_RNONE | SDIO_ERR;
sdio_wait_while_busy(dev);
if (SDDEBUG && SDINFO) {
unsigned c = dev->d_dev->sd_cmd;
unsigned r = dev->d_dev->sd_data;
txstr("CMD0: SEND_GO_IDLE\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
}
// }}}
void sdio_clear_fifo(SDIODRV *dev, unsigned fifo) { // No CMD
// {{{
unsigned phy, k, lglen;
phy = dev->d_dev->sd_phy;
lglen = (phy >> 28);
dev->d_dev->sd_cmd = SDIO_NULLCMD;
if (fifo) {
for(int k=0; k< (1<<lglen); k++)
dev->d_dev->sd_fifb = 0;
} else
for(int k=0; k< (1<<lglen); k++)
dev->d_dev->sd_fifa = 0;
}
// }}}
void sdio_all_send_cid(SDIODRV *dev) { // CMD2
// {{{
unsigned c;
if (SDDEBUG) txstr("CMD2: READ-CID\n");
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_READR2)+2;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
dev->d_CID[0] = dev->d_dev->sd_fifa;
dev->d_CID[1] = dev->d_dev->sd_fifa;
dev->d_CID[2] = dev->d_dev->sd_fifa;
dev->d_CID[3] = dev->d_dev->sd_fifa;
if (SDDEBUG && (c & SDIO_ERR)) {
TRIGGER_SCOPE;
txstr(" SD-ERR: "); txhex(c); txstr("\n");
}
if (SDINFO) {
unsigned r = dev->d_dev->sd_data;
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
sdio_dump_cid(dev);
}
}
// }}}
void sdio_send_cid(SDIODRV *dev) { // CMD10
// {{{
if (SDDEBUG) txstr("SEND-CID\n");
dev->d_dev->sd_data = (dev->d_RCA << 16);
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_READR2) + 10;
sdio_wait_while_busy(dev);
dev->d_CID[0] = dev->d_dev->sd_fifa;
dev->d_CID[1] = dev->d_dev->sd_fifa;
dev->d_CID[2] = dev->d_dev->sd_fifa;
dev->d_CID[3] = dev->d_dev->sd_fifa;
if (SDINFO) {
unsigned c = dev->d_dev->sd_cmd;
unsigned r = dev->d_dev->sd_data;
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
sdio_dump_cid(dev);
}
}
// }}}
void sdio_dump_cid(SDIODRV *dev) {
// {{{
txstr("CID: ");
txhex(dev->d_CID[0]); txstr(":");
txhex(dev->d_CID[1]); txstr(":");
txhex(dev->d_CID[2]); txstr(":");
txhex(dev->d_CID[3]); txstr("\n");
#ifdef STDIO_DEBUG
unsigned sn, md;
sn = dev->d_CID[2];
sn = (sn << 8) | (dev->d_CID[3] >> 24) & 0x0ff;
md = (dev->d_CID[3] >> 8) & 0x0fff;
printf("CID:\n"
"\tManufacturer ID: 0x%02x\n"
"\tApplication ID: %c%c\n"
"\tProduct Name: %c%c%c%c%c\n"
"\tProduct Revision: %x.%x\n"
"\tSerial Number: 0x%0x\n",
(dev->d_CID[0] >> 24)&0x0ff, // MFR ID
(dev->d_CID[0] >> 16)&0x0ff, // APP ID
(dev->d_CID[0] >> 8)&0x0ff,
(dev->d_CID[0] )&0x0ff, // Prod Name[0]
(dev->d_CID[1] >> 24)&0x0ff, // Prod Name[1]
(dev->d_CID[1] >> 16)&0x0ff, // Prod Name[2]
(dev->d_CID[1] >> 8)&0x0ff, // Prod Name[3]
(dev->d_CID[1] )&0x0ff, // Prod Name[4]
(dev->d_CID[2] >> 28)&0x00f, // Revision Hi
(dev->d_CID[2] >> 24)&0x00f, sn); // Lo, and Serial #
printf(
"\tYear of Man.: %d\n"
"\tMonth of Man.: %d\n",
((md>>4)+2000), md&0x0f);
#endif
}
// }}}
uint32_t sdio_send_rca(SDIODRV *dev) { // CMD3
// {{{
unsigned c, r;
if (SDDEBUG) txstr("SEND-RCA\n");
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_READREG)+3;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
if (c & SDIO_ERR) {
TRIGGER_SCOPE;
if (SDDEBUG) {
txstr(" SD-ERR: ");
txhex(c);
txstr("\n");
if (SDINFO)
sdio_dump_err(c);
}
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_READREG)+3;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
if (c & SDIO_ERR) {
if (SDDEBUG) {
txstr(" SD-ERR: ");
txhex(c);
txstr("\n");
if (SDINFO)
sdio_dump_err(c);
}
return 0;
}
}
r = dev->d_dev->sd_data;
if (SDINFO) {
if (!SDDEBUG) txstr("SEND-RCA\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
return dev->d_RCA = (r >> 16)&0x0ffff;
}
// }}}
void sdio_select_card(SDIODRV *dev) { // CMD7
// {{{
unsigned c, r;
dev->d_dev->sd_data = dev->d_RCA << 16;
dev->d_dev->sd_cmd = (SDIO_ERR | SDIO_READREGb) + 7;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
if (SDDEBUG && ((c & SDIO_ERR) || SDINFO)) {
if (c & SDIO_ERR)
TRIGGER_SCOPE;
txstr("CMD7: SELECT_CARD ("); txhex(dev->d_RCA);txstr(")\n");
if (c & SDIO_ERR) {
txstr(" SD-ERR: "); txhex(c); txstr("\n");
sdio_dump_err(c);
}
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
}
// }}}
void sdio_unselect_card(SDIODRV *dev) { // CMD7
// {{{
unsigned c, r;
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR | SDIO_READREGb) + 7;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
if (SDDEBUG && SDINFO) {
// An error is expected, so we don't trigger here on error.
txstr("CMD7: (UN)SELECT_CARD\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
// Clear the (expected) error
dev->d_dev->sd_cmd = SDIO_ERR | SDIO_NULLCMD;
}
// }}}
uint32_t sdio_send_if_cond(SDIODRV *dev, uint32_t ifcond) { // CMD8
// {{{
unsigned c, r;
dev->d_dev->sd_data = ifcond;
dev->d_dev->sd_cmd = SDIO_READREG+8;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
if (SDDEBUG && SDINFO) {
txstr("CMD8: SEND_IF_COND ("); txhex(ifcond); txstr(")\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
return r;
}
// }}}
uint32_t sdio_send_op_cond(SDIODRV *dev, uint32_t opcond) { // ACMD41
// {{{
unsigned c, r;
sdio_send_app_cmd(dev);
// The following should be handled one level above us
// if (phy & SDPHY_1P8VSPT)
// // Declare to the SD card that the PHY is 1.8v capable
// dev->d_dev->sd_data = opcond | S18R;
dev->d_dev->sd_data = opcond;
dev->d_dev->sd_cmd = SDIO_READREG+41;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
dev->d_OCR = r;
if (SDDEBUG && SDINFO) {
txstr("ACMD41: SEND_OP_COND : "); txhex(opcond); txstr("\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
return r;
}
// }}}
void sdio_send_voltage_switch(SDIODRV *dev) { // CMD11
// {{{
unsigned c, r;
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR | SDIO_READREG)+11;
sdio_wait_while_busy(dev);
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
if (SDDEBUG && SDINFO) {
txstr("CMD11: SEND_VOLTAGE_SWITCH : \n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
if (0 == (c & SDIO_ERR)) {
// Switch to 1.8V
unsigned phy, noop;
phy = dev->d_dev->sd_phy;
// We can't quite use SDIOCK_SDR12 here, since we aren't
// switching to 4b mode. That requires an additional command,
// the ACMD6.
phy &= ~SDIOCK_MASK;
phy |= SDPHY_1P8V | SDIOCK_25MHZ | SDPHY_PUSHPULL;
// Must also shut down the clock at this time
dev->d_dev->sd_phy = phy | SDIOCK_SHUTDN;
// Need to wait about 5ms
for(unsigned k=0; k<150000; k++)
noop = dev->d_dev->sd_phy;
// Can then re-enable the clock
dev->d_dev->sd_phy = phy & (~SDIOCK_SHUTDN);
// Then need to wait another 1ms
for(unsigned k=0; k<30000; k++)
noop = dev->d_dev->sd_phy;
while(SDIOCK_25MHZ != (dev->d_dev->sd_phy & 0x0ff))
; // Wait for the clock to change to 25MHz
} else if (SDDEBUG)
// sdio_decode_cmd(c);
sdio_dump_err(c);
// return r;
}
// }}}
static void sdio_send_tuning_block(SDIODRV *dev) { // CMD19
// {{{
unsigned phy, vmask = 0, best_eye=0, best_ph=0,
first_eye=0, eyesz=0, ph;
const unsigned pat[16] = {
0xFF0FFF00, 0xFFCCC3CC, 0xC33CCCFF, 0xFEFFFEEF,
0xFFDFFFDD, 0xFFFBFFFB, 0xBFFF7FFF, 0x77F7BDEF,
0xFFF0FFF0, 0x0FFCCC3C, 0xCC33CCCF, 0xFFEFFFEE,
0xFFFDFFFD, 0xDFFFBFFF, 0xBBFFF7FF, 0xF77F7BDE
};
unsigned rxv[16];
phy = dev->d_dev->sd_phy;
best_ph = (phy >> 16) & 0x1f;
phy &= ~SECTOR_MASK;
phy |= SECTOR_64B;
dev->d_dev->sd_data = 0;
for(ph = 0; ph<31; ph++) {
phy &= ~SDPHY_PHASEMSK;
phy |= (ph << 16);
dev->d_dev->sd_phy = phy;
// We *must* reset any error flags here, since many of these
// phase tests will generate errors in the first place. This
// is just normal.
dev->d_dev->sd_cmd = (SDIO_ERR | SDIO_CMD | SDIO_R1 | SDIO_MEM) + 19;
sdio_wait_while_busy(dev);
if (SDDEBUG && SDINFO) {
// {{{
unsigned c, r;
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
txstr("CMD19: SEND_TUNING_COMMAND : \n");
txstr(" Cmd: "); txhex(c);
if (c & SDIO_ERR)
txstr(" -- FAILED");
txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
txstr(" Phy: "); txhex(phy);
txstr(", Phase = "); txdecimal((phy >> 16)&0x1f);
txstr("\n");
}
// }}}
unsigned vld = 1;
for(int k=0; k<16; k++)
rxv[k] = dev->d_dev->sd_fifa;
for(int k=0; k<16; k++) {
for(int k=0; (k<16) && vld; k++) {
unsigned r;
r = rxv[k];
if (pat[k] != r) {
vld = 0;
break;
}
} if (vld) {
vmask |= (1u<<ph);
if (0 == eyesz)
first_eye = ph;
eyesz++;
} else {
if (eyesz > best_eye) {
best_ph = (ph - first_eye)/2;
best_ph += first_eye;
best_eye = eyesz;
if (SDDEBUG && SDINFO) {
txstr("New best eye: ");
txdecimal(best_ph); txstr(", ");
txdecimal(best_eye); txstr("\n");
}
}
first_eye = 0;
eyesz = 0;
}
}
// Clear any prior errors before continuing
dev->d_dev->sd_cmd = SDIO_ERR | SDIO_NULLCMD;
if (vmask != 0) {
phy &= ~(SDPHY_PHASEMSK | SECTOR_MASK);
phy |= (best_ph << 16) | SECTOR_512B;
dev->d_dev->sd_phy = phy;
}
if (SDINFO && SDDEBUG) {
// {{{
txstr("CMD19: SEND_TUNING_COMMAND, Analysis Complete ----\n");
txstr(" Vld msk: "); txhex(vmask);
if (vmask == 0)
txstr(" -- Failed\n");
else {
txstr("\n BestPh: "); txdecimal(best_ph); txstr("\n");
txstr(" Phy: "); txhex(dev->d_dev->sd_phy); txstr("\n");
}
}
// }}}
// return vmask != 0;
}
// }}}
void sdio_set_bus_width(SDIODRV *dev, uint32_t width) { // ACMD6
// {{{
sdio_send_app_cmd(dev);
dev->d_dev->sd_data = width;
dev->d_dev->sd_cmd = SDIO_READREG+6;
sdio_wait_while_busy(dev);
if (SDDEBUG && SDINFO) {
unsigned c, r;
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
txstr("ACMD6: SET_BUS_WIDTH\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
}
// }}}
void sdio_send_app_cmd(SDIODRV *dev) { // CMD 55
// {{{
dev->d_dev->sd_data = dev->d_RCA << 16;
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_READREG)+55;
sdio_wait_while_busy(dev);
if (SDDEBUG && SDINFO) {
unsigned c, r;
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
txstr("CMD55: SEND_APP_CMD\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
}
// }}}
void sdio_dump_ocr(SDIODRV *dev) {
// {{{
if (SDINFO) {
txstr("READ-OCR: OCR = "); txhex(dev->d_OCR); txstr("\n");
if (0 == (dev->d_OCR & 0x80000000))
txstr(" Card is still powering up\n");
if (dev->d_OCR & 0x40000000)
txstr(" CCS: High capacity support\n");
if (dev->d_OCR & 0x20000000)
txstr(" UHS: UHS-II card\n");
if (dev->d_OCR & 0x01000000)
txstr(" S18A: Switching to 1.8V allowed\n");
#ifdef STDIO_DEBUG
int mxv = 0, mnv = 0;
if (dev->d_OCR & 0x00800000) {
if (mxv == 0||mxv <= 36)
mxv = 36;
if (mnv == 0||mnv >= 35)
mnv = 35;
} if (dev->d_OCR & 0x00400000) {
if (mxv == 0||mxv <= 35)
mxv = 35;
if (mnv == 0||mnv >= 34)
mnv = 34;
} if (dev->d_OCR & 0x00200000) {
if (mxv == 0||mxv <= 34)
mxv = 34;
if (mnv == 0||mnv >= 33)
mnv = 33;
} if (dev->d_OCR & 0x00100000) {
if (mxv == 0||mxv <= 33)
mxv = 33;
if (mnv == 0||mnv >= 32)
mnv = 32;
} if (dev->d_OCR & 0x00080000) {
if (mxv == 0||mxv <= 32)
mxv = 32;
if (mnv == 0||mnv >= 31)
mnv = 31;
} if (dev->d_OCR & 0x00040000) {
if (mxv == 0||mxv <= 31)
mxv = 31;
if (mnv == 0||mnv >= 30)
mnv = 30;
} if (dev->d_OCR & 0x00020000) {
if (mxv == 0||mxv <= 30)
mxv = 30;
if (mnv == 0||mnv >= 29)
mnv = 29;
} if (dev->d_OCR & 0x00010000) {
if (mxv == 0||mxv <= 29)
mxv = 29;
if (mnv == 0||mnv >= 28)
mnv = 28;
} if (dev->d_OCR & 0x00008000) {
if (mxv == 0||mxv <= 28)
mxv = 28;
if (mnv == 0||mnv >= 27)
mnv = 27;
} printf(" Voltage ranges supported: %d.%dV - %d.%dV\n",
(mxv/10), (mxv%10), (mnv/10), (mnv%10));
#else
if (dev->d_OCR & 0x00800000) txstr(" 3.6-3.5 V allowed\n");
if (dev->d_OCR & 0x00400000) txstr(" 3.5-3.4 V allowed\n");
if (dev->d_OCR & 0x00200000) txstr(" 3.4-3.3 V allowed\n");
if (dev->d_OCR & 0x00100000) txstr(" 3.3-3.2 V allowed\n");
if (dev->d_OCR & 0x00080000) txstr(" 3.2-3.1 V allowed\n");
if (dev->d_OCR & 0x00040000) txstr(" 3.1-3.0 V allowed\n");
if (dev->d_OCR & 0x00020000) txstr(" 3.0-2.9 V allowed\n");
if (dev->d_OCR & 0x00010000) txstr(" 2.9-2.8 V allowed\n");
if (dev->d_OCR & 0x00008000) txstr(" 2.8-2.7 V allowed\n");
#endif
}
}
// }}}
void sdio_read_scr(SDIODRV *dev) { // ACMD 51
// {{{
uint32_t phy = dev->d_dev->sd_phy;
phy &= ~SECTOR_MASK;
phy |= (3 << 24); // 64 bits = 8 bytes = 2^3 bytes
dev->d_dev->sd_phy = phy;
sdio_send_app_cmd(dev);
dev->d_dev->sd_data = 0;
dev->d_dev->sd_cmd = (SDIO_ERR|SDIO_MEM|SDIO_READREG)+51;
sdio_wait_while_busy(dev);
if (SDDEBUG && SDINFO) {
// {{{
unsigned c, r;
c = dev->d_dev->sd_cmd;
r = dev->d_dev->sd_data;
txstr("ACMD51: SEND_SCR\n");
txstr(" Cmd: "); txhex(c); txstr("\n");
txstr(" Data: "); txhex(r); txstr("\n");
}
// }}}
if (SDINFO) txstr(" SCR : ");
for(int k=0; k<8; k+= sizeof(uint32_t)) {
unsigned uv;
uv = dev->d_dev->sd_fifa;
if (SDINFO) { txhex(uv); if (k < 4) txstr(":"); }
dev->d_SCR[k + 3] = uv & 0x0ff; uv >>= 8;
dev->d_SCR[k + 2] = uv & 0x0ff; uv >>= 8;
dev->d_SCR[k + 1] = uv & 0x0ff; uv >>= 8;
dev->d_SCR[k + 0] = uv;
} if (SDINFO) txstr("\n");
phy &= ~SECTOR_MASK;
phy |= SECTOR_512B;
dev->d_dev->sd_phy = phy;
if (SDINFO)
sdio_dump_scr(dev);
}
// }}}
void sdio_dump_scr(SDIODRV *dev) {
// {{{
txstr(" SCR_STRUCTURE: "); txhex((dev->d_SCR[0] >> 4)& 0x0f); txstr("\n");
txstr(" SD_SPEC : "); txhex(dev->d_SCR[0]& 0x0f); txstr("\n");
txstr(" STATAFTERERAS: "); txhex((dev->d_SCR[1]&0x80)?1:0); txstr("\n");
txstr(" SD_SECURITY : "); txhex((dev->d_SCR[1]>>4) & 0x07); txstr("\n");
txstr(" SD_BUS_WIDTHS: "); txhex(dev->d_SCR[1] & 0x0f); txstr("\n");
txstr(" EX_SECURITY : "); txhex((dev->d_SCR[2]>>3) & 0x07); txstr("\n");
txstr(" SD_SPEC3 : "); txhex((dev->d_SCR[2] & 0x80) ? 1:0); txstr("\n");
txstr(" SD_SPEC4 : "); txhex((dev->d_SCR[2] & 0x04) ? 1:0); txstr("\n");
txstr(" SD_SPECX : "); txhex(((dev->d_SCR[3]>>6)&0x03)
| ((dev->d_SCR[2]&0x03)<<2)); txstr("\n");
txstr(" CMD_SUPPORT : "); txhex(dev->d_SCR[3] & 0x0f); txstr("\n");
}
// }}}
void sdio_dump_err(unsigned c) {
// {{{
if (SDINFO && (c & SDIO_ERR)) {
if (c & SDIO_REMOVED)
txstr(" Card has been removed\n");
if (c & SDIO_DMAERR)
txstr(" DMA Bus Error\n");
if (c & SDIO_CMDERR) {
if (SDIO_CMDTMOUT == (c & SDIO_CMDECODE))
txstr(" CMD-Timeout\n");
else if (SDIO_CMDCRCER == (c & SDIO_CMDECODE))
txstr(" CMD-CRC Error\n");
else if (SDIO_CMDFRMER == (c & SDIO_CMDECODE))
txstr(" CMD-Frame Error (Bad stop bit)\n");
} else if (c & SDIO_RXERR) {
if (c & SDIO_RXECODE)
txstr(" Rx CRC Error\n");
else
txstr(" Data Watchdog timeout\n");
}
}
}
// }}}
static void sdio_decode_cmd(const uint32_t cmd) {
// {{{
#ifdef STDIO_DEBUG
if (cmd & 0x40)
printf("CMD: 0x%02x\n", cmd & 0x07f);
else if (0x3f == (cmd & 0x3f))
printf("REPLY: (None)\n");
else
printf("REPLY: 0x%02x\n", cmd & 0x07f);
//
if (0 == (cmd & 0x0300))
printf("EXPECT: (No reply)\n");
else if (SDIO_R1 == (cmd & 0x0300))
printf("EXPECT: R1\n");
else if (SDIO_R2 == (cmd & 0x0300))
printf("EXPECT: R2\n");
else if (SDIO_R1b == (cmd & 0x0300))
printf("EXPECT: R1b (R1 w/ Busy)\n");
//
if (cmd & SDIO_MEM) {
if (cmd & SDIO_WRITE)
printf("TYPE: Data WRITE command\n");
else // if (cmd & SDIO_WRITE)
printf("TYPE: Data READ command\n");
}
if (SDIO_FIFO & cmd)
printf("FIFO: B\n");
else
printf("FIFO: A\n");