Impact of L1D Cache Size Change

[DarkC343]

Hello,
I want to explore L1D cache size impact on the overall performance of workloads in QV100 architecture. Since the simulator dynamically changes the L1 associativity in the unified L1/Shared Memory, I think the impact of doubling the set size, associativity or block size is insignificant as I saw in BFS for instance (ie. by changing -gpgpu_cache:dl1). Please guide me on this

[macto94]

I'm also interested in exploring similar aspects, so I'm trying to look into it.
Perhaps, setting the adaptive cache config to false (-gpgpu_adaptive_cache_config 0) and analyzing the impact of L1 size could be an approach?

[JRPan]

It does not change the cache size dynamically. It's changing cache size based on your shared memory usage, which is defined by the programmer.

If you have 128KB unified L1, that is shared memory + L1D cache together. If a kernel uses 32KB shared memory, then the L1D is 96KB.

So L1D cache size is always constant, but maybe not fully 128KB.

[JRPan]

If you don't need shared memory, disabling it does not hurt.