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rsnikhilrsnikhil
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Minimization of diffs w.r.t. Piccolo
1 parent 2ea8aad commit 4c0f7f6

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+59
-20
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3 files changed

+59
-20
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‎builds/Resources/Build_all.mk

+25-17
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
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# This Makefile should be invoked in the 'builds' directory
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88
CPU=Flute
9+
REPO ?= $(HOME)/GitHub/$(CPU)
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.PHONY: help
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help:
@@ -23,31 +24,38 @@ help:
2324
@echo " fixing the C-import functionality."
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2526
.PHONY: build_all
26-
build_all:
27-
make -f Resources/Build_all.mk ARCH=RV32ACIMU SIM=bluesim build_and_test
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make -f Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=bluesim build_and_test
29-
make -f Resources/Build_all.mk ARCH=RV64ACIMU SIM=bluesim build_and_test
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make -f Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=bluesim build_and_test
31-
#
32-
make -f Resources/Build_all.mk ARCH=RV32ACIMU SIM=verilator build_and_test
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make -f Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=verilator build_and_test
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make -f Resources/Build_all.mk ARCH=RV64ACIMU SIM=verilator build_and_test
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make -f Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=verilator build_and_test
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#
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make -f Resources/Build_all.mk ARCH=RV32ACIMU SIM=iverilog build_and_test_iverilog
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make -f Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=iverilog build_and_test_iverilog
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make -f Resources/Build_all.mk ARCH=RV64ACIMU SIM=iverilog build_and_test_iverilog
40-
make -f Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=iverilog build_and_test_iverilog
27+
build_all: build_all_bluesim build_all_verilator build_all_iverilog
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29+
.PHONY: build_all_bluesim
30+
build_all_bluesim:
31+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACIMU SIM=bluesim build_and_test
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make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=bluesim build_and_test
33+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACIMU SIM=bluesim build_and_test
34+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=bluesim build_and_test
35+
36+
.PHONY: build_all_verilator
37+
build_all_verilator:
38+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACIMU SIM=verilator build_and_test
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make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=verilator build_and_test
40+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACIMU SIM=verilator build_and_test
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make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=verilator build_and_test
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43+
.PHONY: build_all_iverilog
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build_all_iverilog:
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make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACIMU SIM=iverilog build_and_test_iverilog
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make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV32ACDFIMSU SIM=iverilog build_and_test_iverilog
47+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACIMU SIM=iverilog build_and_test_iverilog
48+
make -f $(REPO)/builds/Resources/Build_all.mk ARCH=RV64ACDFIMSU SIM=iverilog build_and_test_iverilog
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.PHONY: build_and_test
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build_and_test:
44-
Resources/mkBuild_Dir.py .. $(ARCH) $(SIM)
52+
$(REPO)/builds/Resources/mkBuild_Dir.py $(REPO) $(ARCH) $(SIM)
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logsave build_and_test.log make -C $(ARCH)_$(CPU)_$(SIM) all test isa_tests
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mv build_and_test.log $(ARCH)_$(CPU)_$(SIM)
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.PHONY: build_and_test_iverilog
4957
build_and_test_iverilog:
50-
Resources/mkBuild_Dir.py .. $(ARCH) $(SIM)
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$(REPO)/builds/Resources/mkBuild_Dir.py $(REPO) $(ARCH) $(SIM)
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logsave build_and_test.log make -C $(ARCH)_$(CPU)_$(SIM) all
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mv build_and_test.log $(ARCH)_$(CPU)_$(SIM)
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‎src_Core/CPU/CPU_Stage2.bsv

+28-3
Original file line numberDiff line numberDiff line change
@@ -297,20 +297,45 @@ module mkCPU_Stage2 #(Bit #(4) verbosity,
297297
`ifdef ISA_F
298298
data_to_stage3.rd_in_fpr= upd_fpr;
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300-
// Bypassing FPR value. We are not using dcache.word64 or result
301-
// here as nanboxing has been taken care of in the data being sent
302-
// to stage3
300+
// Bypassing FPR value.
303301
if (upd_fpr) begin
302+
// Choose one of the following two options
303+
304+
// Option 1: longer critical path, since the data is bypassed back into previous stage.
305+
// We use data_to_stage3.rd_val since nanboxing has been done.
306+
// fbypass.bypass_state = ((ostatus == OSTATUS_PIPE) ? BYPASS_RD_RDVAL : BYPASS_RD);
307+
// fbypass.rd_val = data_to_stage3.rd_val;
308+
309+
// Option 2: shorter critical path, since the data is not bypassed into previous stage,
310+
// (the bypassing is effectively delayed until the next stage).
304311
fbypass.bypass_state = BYPASS_RD;
305312
end
306313

307314
// Bypassing GPR value in a FD system
308315
else if (rg_stage2.rd != 0) begin // TODO: is this test necessary?
316+
// Choose one of the following two options
317+
318+
// Option 1: longer critical path, since the data is bypassed back into previous stage.
319+
// We use data_to_stage3.rd_val since nanboxing has been done.
320+
// bypass.bypass_state = ((ostatus == OSTATUS_PIPE) ? BYPASS_RD_RDVAL : BYPASS_RD);
321+
// bypass.rd_val = result;
322+
323+
// Option 2: shorter critical path, since the data is not bypassed into previous stage,
324+
// (the bypassing is effectively delayed until the next stage).
309325
bypass.bypass_state = BYPASS_RD;
310326
end
311327
`else
312328
// Bypassing GPR value in a non-FD system. LD result meant for GPR
313329
if (rg_stage2.rd != 0) begin // TODO: is this test necessary?
330+
// Choose one of the following two options
331+
332+
// Option 1: longer critical path, since the data is bypassed back into previous stage.
333+
// We use data_to_stage3.rd_val since nanboxing has been done.
334+
// bypass.bypass_state = ((ostatus == OSTATUS_PIPE) ? BYPASS_RD_RDVAL : BYPASS_RD);
335+
// bypass.rd_val = result;
336+
337+
// Option 2: shorter critical path, since the data is not bypassed into previous stage,
338+
// (the bypassing is effectively delayed until the next stage).
314339
bypass.bypass_state = BYPASS_RD;
315340
end
316341
`endif

‎src_Testbench/Top/Top_HW_Side.bsv

+6
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,10 @@ module mkTop_HW_Side (Empty) ;
9999

100100
// ----------------
101101
// Start timing the simulation
102+
`ifndef IVERILOG
102103
Bit #(32) cycle_num <- cur_cycle;
103104
c_start_timing (zeroExtend (cycle_num));
105+
`endif
104106

105107
// ----------------
106108
// Open file for Tandem Verification trace output
@@ -146,8 +148,10 @@ module mkTop_HW_Side (Empty) ;
146148
cur_cycle, soc_top.status, soc_top.status);
147149

148150
// End timing the simulation
151+
`ifndef IVERILOG
149152
Bit #(32) cycle_num <- cur_cycle;
150153
c_end_timing (zeroExtend (cycle_num));
154+
`endif
151155

152156
$finish (0);
153157
endrule
@@ -256,8 +260,10 @@ module mkTop_HW_Side (Empty) ;
256260
$display ("Top_HW_Side.rl_debug_client_request_recv: SHUTDOWN");
257261

258262
// End timing the simulation and print simulation speed stats
263+
`ifndef IVERILOG
259264
Bit #(32) cycle_num <- cur_cycle;
260265
c_end_timing (zeroExtend (cycle_num));
266+
`endif
261267

262268
$finish (0);
263269
end

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