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encounter1.log
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encounter1.log
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Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 9.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p058.
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2009. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
*******************************************************************
@(#)CDS: Encounter v09.11-s084_1 (64bit) 04/26/2010 12:41 (Linux 2.6)
@(#)CDS: NanoRoute v09.11-s008 NR100226-1806/USR63-UB (database version 2.30, 93.1.1) {superthreading v1.14}
@(#)CDS: CeltIC v09.11-s011_1 (64bit) 03/04/2010 14:24:46 (Linux 2.6.9-78.0.25.ELsmp)
@(#)CDS: CTE 09.11-s016_1 (64bit) Apr 8 2010 03:29:23 (Linux 2.6.9-78.0.25.ELlargesmp)
@(#)CDS: CPE v09.11-s023
--- Starting "Encounter v09.11-s084_1" on Mon May 4 23:16:55 2015 (mem=59.9M) ---
--- Running on ecegrid-thin2.ecn.purdue.edu (x86_64 w/Linux 2.6.32-504.12.2.el6.x86_64) ---
This version was compiled on Mon Apr 26 12:41:12 PDT 2010.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD> loadConfig ./encounter.conf
Reading config file - ./encounter.conf
**WARN: (ENCEXT-1085): Option 'rda_Input(ui_res_scale)' used in configuration file './encounter.conf' is obsolete. The name will be converted into new format automatically if design is saved and then restored. Alternatively, update the configuration file to use names 'rda_Input(ui_preRoute_res)' and/or 'rda_Input(ui_postRoute_res)' for resistance scale factors to be used at preRoute/postRoute stages of the design . The obsolete name works in this release. But to avoid this warning and to ensure compatibility with future releases, update this option name.
Loading Lef file /package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.lef...
**WARN: (ENCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
Set DBUPerIGU to M2 pitch 2400.
Initializing default via types and wire widths ...
Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Mon May 4 23:17:03 2015
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET cc via 0.150 ;
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET via via2 0.150 ;
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN1 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN2 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN3 GENERATE
viaInitial ends at Mon May 4 23:17:03 2015
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'mapped/Floating_point_co_processor_top.v'
Inserting temporary buffers to remove assignment statements.
Module on_chip_sram_wrapper not defined. Created automatically.
**WARN: (ENCVL-346): Module on_chip_sram_wrapper is not defined in LEF files. It will be treated as an empty module.
Undeclared bus init_file_number in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus dump_file_number in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus start_address in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus last_address in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus address in module on_chip_sram_wrapper ... created as [7:0].
Undeclared bus read_data in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus write_data in module on_chip_sram_wrapper ... created as [31:0].
*** Memory Usage v0.159.2.6.2.1 (Current mem = 419.605M, initial mem = 59.918M) ***
*** End netlist parsing (cpu=0:00:00.6, real=0:00:01.0, mem=419.6M) ***
Set top cell to Floating_point_co_processor_top.
Reading common timing library '/package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.tlf' ...
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'D' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'CLKBUF1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADVDD' in timing library 'osu05_stdcells'.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADGND' in timing library 'osu05_stdcells'.
read 39 cells in library 'osu05_stdcells'
*** End library_loading (cpu=0.00min, mem=0.3M, fe_cpu=0.12min, fe_mem=419.9M) ***
**WARN: (ENCDB-2504): Cell on_chip_sram_wrapper is instantiated in the Verilog netlist, but is not defined.
Mark pin read_data[31] of cell on_chip_sram_wrapper output for net load_data[31] in module Floating_point_co_processor_design
Mark pin read_data[30] of cell on_chip_sram_wrapper output for net load_data[30] in module Floating_point_co_processor_design
Mark pin read_data[29] of cell on_chip_sram_wrapper output for net load_data[29] in module Floating_point_co_processor_design
Mark pin read_data[28] of cell on_chip_sram_wrapper output for net load_data[28] in module Floating_point_co_processor_design
Mark pin read_data[27] of cell on_chip_sram_wrapper output for net load_data[27] in module Floating_point_co_processor_design
Mark pin read_data[26] of cell on_chip_sram_wrapper output for net load_data[26] in module Floating_point_co_processor_design
Mark pin read_data[25] of cell on_chip_sram_wrapper output for net load_data[25] in module Floating_point_co_processor_design
Mark pin read_data[24] of cell on_chip_sram_wrapper output for net load_data[24] in module Floating_point_co_processor_design
Mark pin read_data[23] of cell on_chip_sram_wrapper output for net load_data[23] in module Floating_point_co_processor_design
Mark pin read_data[22] of cell on_chip_sram_wrapper output for net load_data[22] in module Floating_point_co_processor_design
Mark pin read_data[21] of cell on_chip_sram_wrapper output for net load_data[21] in module Floating_point_co_processor_design
Mark pin read_data[20] of cell on_chip_sram_wrapper output for net load_data[20] in module Floating_point_co_processor_design
Mark pin read_data[19] of cell on_chip_sram_wrapper output for net load_data[19] in module Floating_point_co_processor_design
Mark pin read_data[18] of cell on_chip_sram_wrapper output for net load_data[18] in module Floating_point_co_processor_design
Mark pin read_data[17] of cell on_chip_sram_wrapper output for net load_data[17] in module Floating_point_co_processor_design
Mark pin read_data[16] of cell on_chip_sram_wrapper output for net load_data[16] in module Floating_point_co_processor_design
Mark pin read_data[15] of cell on_chip_sram_wrapper output for net load_data[15] in module Floating_point_co_processor_design
Mark pin read_data[14] of cell on_chip_sram_wrapper output for net load_data[14] in module Floating_point_co_processor_design
Mark pin read_data[13] of cell on_chip_sram_wrapper output for net load_data[13] in module Floating_point_co_processor_design
Mark pin read_data[12] of cell on_chip_sram_wrapper output for net load_data[12] in module Floating_point_co_processor_design
Mark pin read_data[11] of cell on_chip_sram_wrapper output for net load_data[11] in module Floating_point_co_processor_design
Mark pin read_data[10] of cell on_chip_sram_wrapper output for net load_data[10] in module Floating_point_co_processor_design
Mark pin read_data[9] of cell on_chip_sram_wrapper output for net load_data[9] in module Floating_point_co_processor_design
Mark pin read_data[8] of cell on_chip_sram_wrapper output for net load_data[8] in module Floating_point_co_processor_design
Mark pin read_data[7] of cell on_chip_sram_wrapper output for net load_data[7] in module Floating_point_co_processor_design
Mark pin read_data[6] of cell on_chip_sram_wrapper output for net load_data[6] in module Floating_point_co_processor_design
Mark pin read_data[5] of cell on_chip_sram_wrapper output for net load_data[5] in module Floating_point_co_processor_design
Mark pin read_data[4] of cell on_chip_sram_wrapper output for net load_data[4] in module Floating_point_co_processor_design
Mark pin read_data[3] of cell on_chip_sram_wrapper output for net load_data[3] in module Floating_point_co_processor_design
Mark pin read_data[2] of cell on_chip_sram_wrapper output for net load_data[2] in module Floating_point_co_processor_design
Mark pin read_data[1] of cell on_chip_sram_wrapper output for net load_data[1] in module Floating_point_co_processor_design
Mark pin read_data[0] of cell on_chip_sram_wrapper output for net load_data[0] in module Floating_point_co_processor_design
Found empty module (on_chip_sram_wrapper).
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell Floating_point_co_processor_top ...
*** Netlist is unique.
** info: there are 449 modules.
** info: there are 49235 stdCell insts.
** info: there are 107 Pad insts.
*** Memory Usage v0.159.2.6.2.1 (Current mem = 450.551M, initial mem = 59.918M) ***
*info - Done with setDoAssign with 1216 assigns removed and 0 assigns could not be removed.
CTE reading timing constraint file 'encounter.pt' ...
INFO (CTE): constraints read successfully
*** Read timing constraints (cpu=0:00:00.0 mem=456.1M) ***
Total number of combinational cells: 26
Total number of sequential cells: 4
Total number of tristate cells: 2
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFX2 BUFX4 CLKBUF1
Total number of usable buffers: 3
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: INVX2 INVX1 INVX4 INVX8
Total number of usable inverters: 4
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells: CLKBUF2 CLKBUF3
Total number of identified usable delay cells: 2
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*info: set bottom ioPad orient R180
Reading IO assignment file "encounter.io" ...
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 120 ps.
PreRoute Cap Scale Factor : 1.00
PreRoute Res Scale Factor : 1.00
PostRoute Cap Scale Factor : 1.00
PostRoute Res Scale Factor : 1.00
PostRoute XCap Scale Factor : 1.00
PreRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PreRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
PostRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PostRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
**WARN: (ENCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
<CMD> floorPlan -r 1.0 0.4 6000 6000 6000 6000
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
<CMD> addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
The power planner created 8 wires.
<CMD> setPlaceMode -congEffort medium
<CMD> placeDesign -inPlaceOpt
*** Starting placeDesign concurrent flow ***
*** Start deleteBufferTree ***
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.2, MEM = 491.9M)
Number of Loop : 0
Start delay calculation (mem=491.949M)...
Delay calculation completed. (cpu=0:00:02.6 real=0:00:02.0 mem=500.145M 0)
*** CDM Built up (cpu=0:00:05.1 real=0:00:05.0 mem= 500.1M) ***
Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
*summary: 2581 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:00:07.3) ***
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
*** Starting "NanoPlace(TM) placement v0.892.2.8.2.1 (mem=503.8M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:00.0 mem=504.8M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:00.0 mem=504.8M) ***
Options: timingDriven ignoreScan ignoreSpare pinGuide gpeffort=medium
**WARN: (ENCDB-2082): Scan chains were not defined, -ignoreScan option will be ignored.
Please first define the scan chains before using this option.
#std cell=46654 #block=0 (0 floating + 0 preplaced) #ioInst=136 #net=48446 #term=161142 #term/net=3.33, #fixedIo=136, #floatIo=0, #fixedPin=105, #floatPin=0
stdCell: 46654 single + 0 double + 0 multi
Total standard cell length = 731.2824 (mm), area = 21.9385 (mm^2)
Average module density = 0.391.
Density for the design = 0.391.
= stdcell_area 304701 (21938472 um^2) / alloc_area 778872 (56078784 um^2).
Pin Density = 0.529.
= total # of pins 161142 / total Instance area 304701.
Iteration 1: Total net bbox = 3.164e+06 (1.80e+06 1.36e+06)
Est. stn bbox = 3.164e+06 (1.80e+06 1.36e+06)
cpu = 0:00:01.3 real = 0:00:01.0 mem = 534.9M
Iteration 2: Total net bbox = 3.164e+06 (1.80e+06 1.36e+06)
Est. stn bbox = 3.164e+06 (1.80e+06 1.36e+06)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 534.9M
Iteration 3: Total net bbox = 3.103e+06 (1.77e+06 1.33e+06)
Est. stn bbox = 3.103e+06 (1.77e+06 1.33e+06)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 534.9M
Iteration 4: Total net bbox = 1.292e+07 (6.24e+06 6.68e+06)
Est. stn bbox = 1.292e+07 (6.24e+06 6.68e+06)
cpu = 0:00:08.5 real = 0:00:09.0 mem = 534.9M
Iteration 5: Total net bbox = 1.213e+07 (5.44e+06 6.68e+06)
Est. stn bbox = 1.213e+07 (5.44e+06 6.68e+06)
cpu = 0:00:07.9 real = 0:00:08.0 mem = 534.9M
Iteration 6: Total net bbox = 1.177e+07 (5.66e+06 6.11e+06)
Est. stn bbox = 1.177e+07 (5.66e+06 6.11e+06)
cpu = 0:00:13.8 real = 0:00:15.0 mem = 537.9M
Iteration 7: Total net bbox = 1.180e+07 (5.69e+06 6.12e+06)
Est. stn bbox = 1.416e+07 (6.59e+06 7.57e+06)
cpu = 0:00:32.4 real = 0:00:33.0 mem = 524.6M
Iteration 8: Total net bbox = 1.180e+07 (5.69e+06 6.11e+06)
Est. stn bbox = 1.415e+07 (6.59e+06 7.57e+06)
cpu = 0:00:27.3 real = 0:00:28.0 mem = 524.5M
Iteration 9: Total net bbox = 1.180e+07 (5.83e+06 5.96e+06)
Est. stn bbox = 1.431e+07 (6.90e+06 7.42e+06)
cpu = 0:00:29.2 real = 0:00:30.0 mem = 527.5M
Iteration 10: Total net bbox = 1.192e+07 (5.89e+06 6.03e+06)
Est. stn bbox = 1.445e+07 (6.96e+06 7.49e+06)
cpu = 0:00:17.0 real = 0:00:17.0 mem = 527.5M
Iteration 11: Total net bbox = 1.176e+07 (5.86e+06 5.91e+06)
Est. stn bbox = 1.443e+07 (7.04e+06 7.39e+06)
cpu = 0:00:33.5 real = 0:00:34.0 mem = 528.5M
Iteration 12: Total net bbox = 1.184e+07 (5.89e+06 5.96e+06)
Est. stn bbox = 1.451e+07 (7.07e+06 7.44e+06)
cpu = 0:00:16.2 real = 0:00:17.0 mem = 528.5M
Iteration 13: Total net bbox = 1.257e+07 (6.27e+06 6.30e+06)
Est. stn bbox = 1.539e+07 (7.57e+06 7.82e+06)
cpu = 0:02:23 real = 0:02:25 mem = 523.5M
Iteration 14: Total net bbox = 1.257e+07 (6.27e+06 6.30e+06)
Est. stn bbox = 1.539e+07 (7.57e+06 7.82e+06)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 525.5M
Iteration 15: Total net bbox = 1.283e+07 (6.49e+06 6.34e+06)
Est. stn bbox = 1.568e+07 (7.81e+06 7.87e+06)
cpu = 0:00:00.9 real = 0:00:01.0 mem = 525.5M
*** cost = 1.283e+07 (6.49e+06 6.34e+06) (cpu for global=0:04:59) real=0:05:05***
Core Placement runtime cpu: 0:03:54 real: 0:03:58
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode. (cpu=0:00:03.7, real=0:00:04.0)
move report: preRPlace moves 2381 insts, mean move: 5.73 um, max move: 51.60 um
max move on inst (I0/FP_PROCESSOR/LOAD/reg_out_reg[16]): (10406.40, 6300.00) --> (10428.00, 6330.00)
Placement tweakage begins.
wire length = 1.283e+07 = 6.491e+06 H + 6.343e+06 V
wire length = 1.249e+07 = 6.173e+06 H + 6.321e+06 V
Placement tweakage ends.
move report: wireLenOpt moves 9749 insts, mean move: 27.87 um, max move: 98.40 um
max move on inst (I0/FP_PROCESSOR/SIN/ADDX3/LARGE_EXPSEL/U2): (7413.60, 7440.00) --> (7512.00, 7440.00)
move report: rPlace moves 11670 insts, mean move: 24.14 um, max move: 98.40 um
max move on inst (I0/FP_PROCESSOR/SIN/ADDX3/LARGE_EXPSEL/U2): (7413.60, 7440.00) --> (7512.00, 7440.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 98.40 um
inst (I0/FP_PROCESSOR/SIN/ADDX3/LARGE_EXPSEL/U2) with max move: (7413.6, 7440) -> (7512, 7440)
mean (X+Y) = 24.14 um
Total instances flipped for WireLenOpt: 732
Total instances flipped, including legalization: 22882
Total instances moved : 11670
*** cpu=0:00:05.5 mem=539.3M mem(used)=21.2M***
Total net length = 1.250e+07 (6.173e+06 6.323e+06) (ext = 0.000e+00)
*** End of Placement (cpu=0:05:10, real=0:05:16, mem=538.2M) ***
default core: bins with density > 0.75 = 0.769 % ( 5 / 650 )
*** Free Virtual Timing Model ...(mem=522.4M)
Starting IO pin assignment...
**WARN: (ENCSP-9025): No scan chain specified/traced.
setAnalysisMode -domain allClockDomain -checkType setup -skew true -usefulSkew false -log true -warn true -caseAnalysis true -sequentialConstProp false -moduleIOCstr true -clockPropagation forcedIdeal -clkSrcPath false -timingSelfLoopsNoSkew false -asyncChecks async -useOutputPinCap true -latch true -latchDelayCalIteration 2 -timeBorrowing true -latchFullDelayCal false -clockGatingCheck true -enableMultipleDriveNet true -analysisType single -cppr false -clkNetsMarking beforeConstProp -honorVirtualPartition false -honorClockDomains true
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell PADVDD is dont_touch but not dont_use
Cell PADNC is dont_touch but not dont_use
Cell PADGND is dont_touch but not dont_use
Cell PADFC is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 521.4M **
Added -handlePreroute to trialRouteMode
*** optDesign -preCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Setup Target Slack: user slack 0.0; extra slack 0.1
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.100
*info: Hold target slack is 0.000
*** CTE mode ***
*** Starting trialRoute (mem=521.4M) ***
There are 0 pin guide points passed to trialRoute.
**WARN: (ENCTR-2325): 64 nets connect a pad term to a fterm without geometry and will not be routed.
Options: -handlePreroute -noPinGuide
Nr of prerouted/Fixed nets = 105
routingBox: (1200 1500) (20106000 20068500)
coreBox: (6300000 6300000) (13807200 13770000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=17/1439
Phase 1a route (0:00:00.8 562.4M):
Est net length = 1.498e+07um = 7.561e+06H + 7.417e+06V
Usage: (12.6%H 9.0%V) = (8.359e+06um 1.157e+07um) = (668356 381816)
Obstruct: 5807 = 1652 (0.4%H) + 4155 (1.0%V)
Overflow: 26939 = 6299 (1.53% H) + 20640 (5.03% V)
Number obstruct path=145 reroute=0
Phase 1b route (0:00:00.5 564.9M):
Usage: (12.6%H 9.0%V) = (8.353e+06um 1.159e+07um) = (667875 382322)
Overflow: 24760 = 4586 (1.11% H) + 20173 (4.92% V)
Phase 1c route (0:00:00.3 564.9M):
Usage: (12.6%H 9.0%V) = (8.345e+06um 1.161e+07um) = (667205 383143)
Overflow: 22059 = 3213 (0.78% H) + 18846 (4.60% V)
Phase 1d route (0:00:00.4 566.0M):
Usage: (12.7%H 9.1%V) = (8.392e+06um 1.175e+07um) = (671058 387544)
Overflow: 14832 = 1525 (0.37% H) + 13307 (3.25% V)
Phase 1e route (0:00:00.9 567.6M):
Usage: (12.7%H 9.4%V) = (8.436e+06um 1.203e+07um) = (673569 397007)
Overflow: 9004 = 82 (0.02% H) + 8922 (2.18% V)
Phase 1f route (0:00:00.9 567.6M):
Usage: (12.9%H 9.4%V) = (8.564e+06um 1.211e+07um) = (683683 399685)
Overflow: 4943 = 31 (0.01% H) + 4912 (1.20% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 3 0.00%
-2: 0 0.00% 266 0.06%
-1: 31 0.01% 4531 1.11%
--------------------------------------
0: 4227 1.02% 34620 8.44%
1: 9238 2.24% 29489 7.19%
2: 11772 2.85% 25684 6.26%
3: 13764 3.34% 21520 5.25%
4: 16071 3.90% 19054 4.65%
5: 17453 4.23% 186161 45.40%
6: 18685 4.53% 892 0.22%
7: 19254 4.67% 12 0.00%
8: 17658 4.28% 35 0.01%
9: 16176 3.92% 28 0.01%
10: 54020 13.09% 8 0.00%
11: 163 0.04% 23 0.01%
12: 310 0.08% 42 0.01%
13: 175 0.04% 1 0.00%
14: 337 0.08% 20 0.00%
15: 120054 29.10% 48 0.01%
16: 93155 22.58% 25 0.01%
17: 0 0.00% 26 0.01%
18: 0 0.00% 73 0.02%
19: 0 0.00% 845 0.21%
20: 0 0.00% 86634 21.13%
Global route (cpu=3.9s real=4.0s 564.9M)
*** After '-updateRemainTrks' operation:
Usage: (12.9%H 9.4%V) = (8.564e+06um 1.211e+07um) = (683683 399685)
Overflow: 4943 = 31 (0.01% H) + 4912 (1.20% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 3 0.00%
-2: 0 0.00% 266 0.06%
-1: 31 0.01% 4531 1.11%
--------------------------------------
0: 4227 1.02% 34620 8.44%
1: 9238 2.24% 29489 7.19%
2: 11772 2.85% 25684 6.26%
3: 13764 3.34% 21520 5.25%
4: 16071 3.90% 19054 4.65%
5: 17453 4.23% 186161 45.40%
6: 18685 4.53% 892 0.22%
7: 19254 4.67% 12 0.00%
8: 17658 4.28% 35 0.01%
9: 16176 3.92% 28 0.01%
10: 54020 13.09% 8 0.00%
11: 163 0.04% 23 0.01%
12: 310 0.08% 42 0.01%
13: 175 0.04% 1 0.00%
14: 337 0.08% 20 0.00%
15: 120054 29.10% 48 0.01%
16: 93155 22.58% 25 0.01%
17: 0 0.00% 26 0.01%
18: 0 0.00% 73 0.02%
19: 0 0.00% 845 0.21%
20: 0 0.00% 86634 21.13%
*** Completed Phase 1 route (0:00:04.6 555.0M) ***
Total length: 1.553e+07um, number of vias: 337435
M1(H) length: 0.000e+00um, number of vias: 160839
M2(V) length: 7.942e+06um, number of vias: 176596
M3(H) length: 7.586e+06um
*** Completed Phase 2 route (0:00:04.3 575.0M) ***
*** Finished all Phases (cpu=0:00:09.2 mem=575.0M) ***
Peak Memory Usage was 564.4M
*** Finished trialRoute (cpu=0:00:09.7 mem=575.0M) ***
Extraction called for design 'Floating_point_co_processor_top' of instances=46790 and nets=49940 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 575.039M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 587.8M)
Number of Loop : 0
Start delay calculation (mem=587.820M)...
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M3_M2' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M2_M1' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
Delay calculation completed. (cpu=0:00:05.7 real=0:00:06.0 mem=590.898M 4)
*** CDM Built up (cpu=0:00:07.9 real=0:00:08.0 mem= 590.9M) ***
Info: 105 io nets excluded
Info: 2 clock nets excluded from IPO operation.
Netlist preparation processing...
Removed 1826 instances
*info: Marking 0 isolation instances dont touch
*info: Marking 0 level shifter instances dont touch
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:05:50 mem=603.8M) ***
*** Finished delays update (0:05:58 mem=597.3M) ***
**optDesign ... cpu = 0:00:33, real = 0:00:34, mem = 597.4M **
*info: Start fixing DRV (Mem = 597.39M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -sensitivity -backward -reduceBuffer -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (597.4M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1772 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.7, MEM=597.4M) ***
*info: There are 3 candidate Buffer cells
*info: There are 4 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.373972
Start fixing design rules ... (0:00:00.7 601.4M)
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC60_npaddr_0_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC61_npaddr_0_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX4.
Phase 1 (2) Starts......
Phase 2 Starts......
Done fixing design rule (0:00:24.3 612.7M)
Summary:
1660 buffers added on 1266 nets (with 873 drivers resized)
Density after buffering = 0.382850
*** Completed dpFixDRCViolation (0:00:25.4 612.3M)
Re-routed 3779 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=46624 and nets=50177 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 612.289M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 606.0M)
Number of Loop : 0
Start delay calculation (mem=605.977M)...
Delay calculation completed. (cpu=0:00:05.3 real=0:00:06.0 mem=608.957M 0)
*** CDM Built up (cpu=0:00:07.6 real=0:00:08.0 mem= 609.0M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 4
*info: Max tran violations: 0
*info: Prev Max cap violations: 1400
*info: Prev Max tran violations: 0
*info:
*info: Completed fixing DRV (CPU Time = 0:00:36, Mem = 608.96M).
**optDesign ... cpu = 0:01:09, real = 0:01:12, mem = 609.0M **
*** Starting optFanout (609.0M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1772 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.7, MEM=609.0M) ***
Start fixing timing ... (0:00:00.6 609.0M)
Start clock batches slack = -5.802ns
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC1904_npaddr_1_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC1905_npaddr_1_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
End batches slack = -3.900ns
*info: Buffered 0 large fanout net (> 100 terms)
Done fixing timing (0:00:24.8 616.8M)
Summary:
722 buffers added on 408 nets (with 1581 drivers resized)
378 nets rebuffered with 409 inst removed and 646 inst added
Density after buffering = 0.388817
*** Completed optFanout (0:00:25.8 616.8M)
Re-routed 34 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=46937 and nets=50490 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 616.785M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 609.5M)
Number of Loop : 0
Start delay calculation (mem=609.496M)...
Delay calculation completed. (cpu=0:00:05.4 real=0:00:06.0 mem=612.512M 0)
*** CDM Built up (cpu=0:00:07.7 real=0:00:08.0 mem= 612.5M) ***
**optDesign ... cpu = 0:01:44, real = 0:01:47, mem = 612.5M **
*** Timing NOT met, worst failing slack is -4.137
*** Check timing (0:00:00.8)
************ Recovering area ***************
Info: 105 io nets excluded
Info: 2 clock nets excluded from IPO operation.
*** Starting Area Reclaim ***
** Density before area reclaim = 38.711% **
*** starting 1-st reclaim pass: 43030 instances
*** starting 2-nd reclaim pass: 42877 instances
*** starting 3-rd reclaim pass: 12501 instances
*** starting 4-th reclaim pass: 828 instances
*** starting 5-th reclaim pass: 39 instances
** Area Reclaim Summary: Buffer Deletion = 31 Declone = 122 Downsize = 2125 **
** Density Change = 0.077% **
** Density after area reclaim = 38.634% **
*** Finished Area Reclaim (0:00:16.2) ***
*** Starting sequential cell resizing ***
density before resizing = 38.634%
*summary: 0 instances changed cell type
density after resizing = 38.634%
*** Finish sequential cell resizing (cpu=0:00:02.0 mem=617.3M) ***
density before resizing = 38.634%
* summary of transition time violation fixes:
*summary: 230 instances changed cell type
density after resizing = 38.689%
*** Starting trialRoute (mem=588.2M) ***
There are 0 pin guide points passed to trialRoute.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 196
routingBox: (1200 1500) (20106000 20068500)
coreBox: (6300000 6300000) (13807200 13770000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=17/1439
Phase 1a route (0:00:00.7 599.6M):
Est net length = 1.454e+07um = 7.339e+06H + 7.203e+06V
Usage: (12.2%H 8.8%V) = (8.107e+06um 1.127e+07um) = (647363 371789)
Obstruct: 5792 = 1652 (0.4%H) + 4140 (1.0%V)
Overflow: 24172 = 5379 (1.30% H) + 18793 (4.58% V)
Number obstruct path=151 reroute=0
Phase 1b route (0:00:00.4 601.7M):
Usage: (12.2%H 8.8%V) = (8.101e+06um 1.129e+07um) = (646879 372290)
Overflow: 22142 = 3716 (0.90% H) + 18426 (4.49% V)
Phase 1c route (0:00:00.3 601.7M):
Usage: (12.2%H 8.8%V) = (8.088e+06um 1.131e+07um) = (645818 373017)
Overflow: 19784 = 2581 (0.63% H) + 17203 (4.20% V)
Phase 1d route (0:00:00.4 602.7M):
Usage: (12.3%H 8.9%V) = (8.131e+06um 1.143e+07um) = (649343 377001)
Overflow: 13228 = 1303 (0.32% H) + 11925 (2.91% V)
Phase 1e route (0:00:00.7 603.5M):
Usage: (12.3%H 9.1%V) = (8.171e+06um 1.165e+07um) = (652503 384349)
Overflow: 8532 = 72 (0.02% H) + 8461 (2.06% V)
Phase 1f route (0:00:00.8 604.5M):
Usage: (12.5%H 9.1%V) = (8.284e+06um 1.175e+07um) = (661708 387759)
Overflow: 4618 = 28 (0.01% H) + 4590 (1.12% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 1 0.00%
-2: 0 0.00% 217 0.05%
-1: 28 0.01% 4281 1.04%
--------------------------------------
0: 3568 0.86% 32950 8.04%
1: 8356 2.03% 28645 6.99%
2: 11052 2.68% 25918 6.32%
3: 13530 3.28% 21716 5.30%
4: 15882 3.85% 19403 4.73%
5: 17725 4.30% 188121 45.88%
6: 18919 4.59% 922 0.22%
7: 19413 4.71% 13 0.00%
8: 17115 4.15% 28 0.01%
9: 15205 3.69% 18 0.00%
10: 57556 13.95% 10 0.00%
11: 164 0.04% 21 0.01%
12: 309 0.07% 36 0.01%
13: 175 0.04% 4 0.00%
14: 577 0.14% 14 0.00%
15: 119975 29.08% 28 0.01%
16: 92994 22.54% 17 0.00%
17: 0 0.00% 13 0.00%
18: 0 0.00% 46 0.01%
19: 0 0.00% 821 0.20%
20: 0 0.00% 86812 21.17%
Global route (cpu=3.2s real=4.0s 602.3M)
*** After '-updateRemainTrks' operation:
Usage: (12.5%H 9.1%V) = (8.284e+06um 1.175e+07um) = (661708 387759)
Overflow: 4618 = 28 (0.01% H) + 4590 (1.12% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 1 0.00%
-2: 0 0.00% 217 0.05%
-1: 28 0.01% 4281 1.04%
--------------------------------------
0: 3568 0.86% 32950 8.04%
1: 8356 2.03% 28645 6.99%
2: 11052 2.68% 25918 6.32%
3: 13530 3.28% 21716 5.30%
4: 15882 3.85% 19403 4.73%
5: 17725 4.30% 188121 45.88%
6: 18919 4.59% 922 0.22%
7: 19413 4.71% 13 0.00%
8: 17115 4.15% 28 0.01%
9: 15205 3.69% 18 0.00%
10: 57556 13.95% 10 0.00%
11: 164 0.04% 21 0.01%
12: 309 0.07% 36 0.01%
13: 175 0.04% 4 0.00%
14: 577 0.14% 14 0.00%
15: 119975 29.08% 28 0.01%
16: 92994 22.54% 17 0.00%
17: 0 0.00% 13 0.00%
18: 0 0.00% 46 0.01%
19: 0 0.00% 821 0.20%
20: 0 0.00% 86812 21.17%
*** Completed Phase 1 route (0:00:03.8 592.2M) ***
Total length: 1.503e+07um, number of vias: 325081
M1(H) length: 2.808e+02um, number of vias: 156667
M2(V) length: 7.680e+06um, number of vias: 168414
M3(H) length: 7.354e+06um
*** Completed Phase 2 route (0:00:03.8 613.2M) ***
*** Finished all Phases (cpu=0:00:07.9 mem=613.2M) ***
Peak Memory Usage was 601.7M
*** Finished trialRoute (cpu=0:00:08.4 mem=613.2M) ***
Extraction called for design 'Floating_point_co_processor_top' of instances=46784 and nets=50344 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 598.957M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 610.2M)
Number of Loop : 0
Start delay calculation (mem=610.234M)...
Delay calculation completed. (cpu=0:00:05.7 real=0:00:05.0 mem=612.816M 0)
*** CDM Built up (cpu=0:00:08.2 real=0:00:08.0 mem= 612.8M) ***
**optDesign ... cpu = 0:02:22, real = 0:02:27, mem = 612.8M **
*info: Start fixing DRV (Mem = 612.82M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -sensitivity -backward -reduceBuffer -secondPreCtsDrv -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (612.8M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1783 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.7, MEM=612.8M) ***
Start fixing design rules ... (0:00:00.7 613.8M)
Done fixing design rule (0:00:02.9 613.8M)
Summary:
103 buffers added on 96 nets (with 80 drivers resized)
Density after buffering = 0.387400
*** Completed dpFixDRCViolation (0:00:03.9 612.9M)
Re-routed 368 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=46887 and nets=50447 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 612.852M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.2, MEM = 609.8M)
Number of Loop : 0
Start delay calculation (mem=609.836M)...
Delay calculation completed. (cpu=0:00:05.5 real=0:00:06.0 mem=612.852M 0)
*** CDM Built up (cpu=0:00:07.8 real=0:00:08.0 mem= 612.9M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 0
*info: Prev Max cap violations: 9
*info: Prev Max tran violations: 0
*info:
*info: Completed fixing DRV (CPU Time = 0:00:14, Mem = 612.85M).
**optDesign ... cpu = 0:02:36, real = 0:02:41, mem = 612.9M **
*** Timing NOT met, worst failing slack is -3.489
*** Check timing (0:00:00.8)
*** Starting optCritPath ***
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1783 no-driver nets excluded.
Density : 0.3874
Max route overflow : 0.0112
Current slack : -3.489 ns, density : 0.3874
Current slack : -3.459 ns, density : 0.3874
Current slack : -3.459 ns, density : 0.3874
Current slack : -3.459 ns, density : 0.3874
Current slack : -3.271 ns, density : 0.3874
Current slack : -3.271 ns, density : 0.3874
Current slack : -3.262 ns, density : 0.3874
Current slack : -3.262 ns, density : 0.3874
Current slack : -3.262 ns, density : 0.3874
Current slack : -3.235 ns, density : 0.3874
Current slack : -3.235 ns, density : 0.3874
Current slack : -3.235 ns, density : 0.3874
Current slack : -2.816 ns, density : 0.3875
Current slack : -2.816 ns, density : 0.3875
Current slack : -2.660 ns, density : 0.3876
Current slack : -2.660 ns, density : 0.3876
Current slack : -2.660 ns, density : 0.3876
Current slack : -2.620 ns, density : 0.3876
Current slack : -2.464 ns, density : 0.3879
Current slack : -2.450 ns, density : 0.3879
Current slack : -2.450 ns, density : 0.3879
Current slack : -2.439 ns, density : 0.3879
Current slack : -2.319 ns, density : 0.3882
Current slack : -2.315 ns, density : 0.3882
Current slack : -2.315 ns, density : 0.3882
Current slack : -2.284 ns, density : 0.3882
Current slack : -2.205 ns, density : 0.3884
Current slack : -2.181 ns, density : 0.3884
Current slack : -2.181 ns, density : 0.3884
Current slack : -2.101 ns, density : 0.3884
Current slack : -2.061 ns, density : 0.3887
Current slack : -2.056 ns, density : 0.3887
Current slack : -2.056 ns, density : 0.3887
Current slack : -2.056 ns, density : 0.3887
Current slack : -2.052 ns, density : 0.3891
Current slack : -2.052 ns, density : 0.3893
Current slack : -1.997 ns, density : 0.3900
Current slack : -1.996 ns, density : 0.3900
Current slack : -1.897 ns, density : 0.3906
Current slack : -1.897 ns, density : 0.3907
Current slack : -1.876 ns, density : 0.3917
Current slack : -1.876 ns, density : 0.3918
Current slack : -1.875 ns, density : 0.3918
Current slack : -1.796 ns, density : 0.3922
Current slack : -1.754 ns, density : 0.3922
Current slack : -1.754 ns, density : 0.3922
Current slack : -1.754 ns, density : 0.3922
Current slack : -1.754 ns, density : 0.3922
Current slack : -1.716 ns, density : 0.4000
Current slack : -1.716 ns, density : 0.4000
Current slack : -1.716 ns, density : 0.4000
Current slack : -1.691 ns, density : 0.4000
Current slack : -1.690 ns, density : 0.4000
Current slack : -1.690 ns, density : 0.4000
Current slack : -1.689 ns, density : 0.4000
Current slack : -1.679 ns, density : 0.4001
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:02:19 mem=628.8M) ***
*** Finished delays update (0:02:29 mem=626.3M) ***
Current slack : -1.664 ns, density : 0.4002
Current slack : -1.659 ns, density : 0.4002
Current slack : -1.658 ns, density : 0.4003
Current slack : -1.658 ns, density : 0.4003
Current slack : -1.649 ns, density : 0.4003
Current slack : -1.649 ns, density : 0.4003
Current slack : -1.619 ns, density : 0.4004
Current slack : -1.619 ns, density : 0.4004
Current slack : -1.619 ns, density : 0.4004
Current slack : -1.618 ns, density : 0.4004
Current slack : -1.604 ns, density : 0.4007
Current slack : -1.599 ns, density : 0.4007
Current slack : -1.599 ns, density : 0.4009
Current slack : -1.595 ns, density : 0.4074
Current slack : -1.595 ns, density : 0.4075
Current slack : -1.583 ns, density : 0.4077
Current slack : -1.514 ns, density : 0.4077
Current slack : -1.514 ns, density : 0.4076
Current slack : -1.514 ns, density : 0.4075
Current slack : -1.512 ns, density : 0.4075
Current slack : -1.512 ns, density : 0.4075
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:03:58 mem=635.9M) ***
*** Finished delays update (0:04:07 mem=635.4M) ***
Current slack : -1.523 ns, density : 0.4075
Current slack : -1.523 ns, density : 0.4075
Current slack : -1.519 ns, density : 0.4075
Current slack : -1.519 ns, density : 0.4075
Current slack : -1.502 ns, density : 0.4077
Current slack : -1.497 ns, density : 0.4078
Current slack : -1.493 ns, density : 0.4078
Current slack : -1.493 ns, density : 0.4078
Current slack : -1.493 ns, density : 0.4077
Current slack : -1.493 ns, density : 0.4078
Current slack : -1.488 ns, density : 0.4124
Current slack : -1.488 ns, density : 0.4124
Current slack : -1.485 ns, density : 0.4124
Current slack : -1.485 ns, density : 0.4124
Current slack : -1.482 ns, density : 0.4124
Current slack : -1.482 ns, density : 0.4124
Current slack : -1.482 ns, density : 0.4124
Current slack : -1.482 ns, density : 0.4124
Current slack : -1.478 ns, density : 0.4125
Current slack : -1.434 ns, density : 0.4124
Current slack : -1.434 ns, density : 0.4125
Current slack : -1.428 ns, density : 0.4125
Current slack : -1.428 ns, density : 0.4125
Current slack : -1.428 ns, density : 0.4125
Current slack : -1.428 ns, density : 0.4125
Current slack : -1.375 ns, density : 0.4125
Current slack : -1.375 ns, density : 0.4125
Current slack : -1.375 ns, density : 0.4125
Current slack : -1.375 ns, density : 0.4125
Current slack : -1.375 ns, density : 0.4126
Current slack : -1.368 ns, density : 0.4126
Current slack : -1.368 ns, density : 0.4127
Current slack : -1.366 ns, density : 0.4185
Current slack : -1.366 ns, density : 0.4188
Current slack : -1.351 ns, density : 0.4189
Current slack : -1.327 ns, density : 0.4189
Current slack : -1.327 ns, density : 0.4188
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4187
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:06:51 mem=645.1M) ***
*** Finished delays update (0:07:03 mem=644.6M) ***
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4187
Current slack : -1.327 ns, density : 0.4189
Current slack : -1.321 ns, density : 0.4189
Current slack : -1.321 ns, density : 0.4189
Current slack : -1.321 ns, density : 0.4189
Current slack : -1.321 ns, density : 0.4189
Current slack : -1.321 ns, density : 0.4189
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.318 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.316 ns, density : 0.4224
Current slack : -1.313 ns, density : 0.4224
Current slack : -1.313 ns, density : 0.4224
Current slack : -1.313 ns, density : 0.4224
Current slack : -1.314 ns, density : 0.4224
Current slack : -1.315 ns, density : 0.4225
Current slack : -1.315 ns, density : 0.4224
Current slack : -1.315 ns, density : 0.4224
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:08:24 mem=647.2M) ***
*** Finished delays update (0:08:33 mem=646.6M) ***
post refinePlace cleanup
post refinePlace cleanup
**WARN: (ENCOPT-3034): Optimization process capabilities limited due to 534 assigned nets
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:08:36 mem=647.1M) ***
*** Finished delays update (0:08:45 mem=646.6M) ***
*** Done optCritPath (0:08:47 646.61M) ***
**optDesign ... cpu = 0:11:25, real = 0:11:41, mem = 646.6M **
*** Starting trialRoute (mem=646.6M) ***
There are 0 pin guide points passed to trialRoute.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 377
routingBox: (1200 1500) (20106000 20068500)
coreBox: (6300000 6300000) (13807200 13770000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=17/1925
Phase 1a route (0:00:00.7 656.1M):
Est net length = 1.537e+07um = 7.755e+06H + 7.619e+06V
Usage: (13.0%H 9.6%V) = (8.588e+06um 1.240e+07um) = (687420 409430)
Obstruct: 5465 = 1652 (0.4%H) + 3813 (0.9%V)
Overflow: 31026 = 7664 (1.86% H) + 23362 (5.69% V)
Number obstruct path=109 reroute=0
Phase 1b route (0:00:00.7 657.1M):