This repository presents a verification test case for an asynchronous FIFO based on Systemverilog Object Oriented concepts and also UVM. The general architecture and implementation of the code has been taken from the UVM primer (Ray Salemi):
https://github.com/rdsalemi/uvmprimer
However the presented verification code in this test case is manipulated to be fitted for the special use case of an asynchronous FIFO.
The RTL source code for the asynchronous FIFO is taken from (Jason Yu):
http://www.verilogpro.com/asynchronous-fifo-design/
If you'd like to add or improve this software design, your contribution is welcome!
This repository is released under the MIT license. In short, this means you are free to use this software in any personal, open-source or commercial projects. Attribution is optional but appreciated.