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mx6.h
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mx6.h
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#define MX6
/* Register definitions */
#define URXD 0x0 /* Receiver Register */
#define UTXD 0x40 /* Transmitter Register */
#define UCR1 0x80 /* Control Register 1 */
#define UCR2 0x84 /* Control Register 2 */
#define UCR3 0x88 /* Control Register 3 */
#define UCR4 0x8c /* Control Register 4 */
#define UFCR 0x90 /* FIFO Control Register */
#define USR1 0x94 /* Status Register 1 */
#define USR2 0x98 /* Status Register 2 */
#define UESC 0x9c /* Escape Character Register */
#define UTIM 0xa0 /* Escape Timer Register */
#define UBIR 0xa4 /* BRM Incremental Register */
#define UBMR 0xa8 /* BRM Modulator Register */
#define UBRC 0xac /* Baud Rate Count Register */
#define UTS 0xb4 /* UART Test Register (mx31) */
/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY (1<<15)
#define URXD_ERR (1<<14)
#define URXD_OVRRUN (1<<13)
#define URXD_FRMERR (1<<12)
#define URXD_BRK (1<<11)
#define URXD_PRERR (1<<10)
#define URXD_RX_DATA (0xFF)
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
#define UCR1_IREN (1<<7) /* Infrared interface enable */
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
#define UCR1_SNDBRK (1<<4) /* Send break */
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#define UCR1_DOZE (1<<1) /* Doze */
#define UCR1_UARTEN (1<<0) /* UART enabled */
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
#define UCR2_CTSC (1<<13) /* CTS pin control */
#define UCR2_CTS (1<<12) /* Clear to send */
#define UCR2_ESCEN (1<<11) /* Escape enable */
#define UCR2_PREN (1<<8) /* Parity enable */
#define UCR2_PROE (1<<7) /* Parity odd/even */
#define UCR2_STPB (1<<6) /* Stop */
#define UCR2_WS (1<<5) /* Word size */
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
#define UCR2_RXEN (1<<1) /* Receiver enabled */
#define UCR2_SRST (1<<0) /* SW reset */
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN (1<<12) /* Parity enable */
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
#define UCR3_DSR (1<<10) /* Data set ready */
#define UCR3_DCD (1<<9) /* Data carrier detect */
#define UCR3_RI (1<<8) /* Ring indicator */
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
#define UCR4_IRSC (1<<5) /* IR special case */
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
#define USR1_RTSD (1<<12) /* RTS delta */
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
#define USR2_IDLE (1<<12) /* Idle condition */
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
#define USR2_WAKE (1<<7) /* Wake */
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
#define USR2_TXDC (1<<3) /* Transmitter complete */
#define USR2_BRCD (1<<2) /* Break condition */
#define USR2_ORE (1<<1) /* Overrun error */
#define USR2_RDR (1<<0) /* Recv data ready */
#define UTS_FRCPERR (1<<13) /* Force parity error */
#define UTS_LOOP (1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
#define UTS_TXFULL (1<<4) /* TxFIFO full */
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
#define PAD_CTL_HYS (1 << 16)
#define PAD_CTL_PUS_47K_UP (1 << 14)
#define PAD_CTL_PUS_100K_UP (2 << 14)
#define PAD_CTL_PUE (1 << 13)
#define PAD_CTL_PKE (1 << 12)
#define PAD_CTL_SPEED_LOW (1 << 6)
#define PAD_CTL_SPEED_MED (2 << 6)
#define PAD_CTL_DSE_DISABLE (0 << 3)
#define PAD_CTL_DSE_240ohm (1 << 3)
#define PAD_CTL_DSE_120ohm (2 << 3)
#define PAD_CTL_DSE_80ohm (3 << 3)
#define PAD_CTL_DSE_60ohm (4 << 3)
#define PAD_CTL_DSE_48ohm (5 << 3)
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
#define writel(v, a) (*(volatile unsigned int *)(a)) = v
#define __REG(x) (*((volatile u32 *)(x)))
#define AIPS1_ARB_BASE_ADDR 0x02000000
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
#define CLK_32KHZ 32768 /* 32Khz input */
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define UART_PHYS (ATZ1_BASE_ADDR + 0x20000)
/* General purpose timers registers */
struct mxc_gpt {
unsigned int control;
unsigned int prescaler;
unsigned int status;
unsigned int nouse[6];
unsigned int counter;
};
static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
struct aipstz_regs {
u32 mprot0;
u32 mprot1;
u32 rsvd[0xe];
u32 opacr0;
u32 opacr1;
u32 opacr2;
u32 opacr3;
u32 opacr4;
};
struct anatop_regs {
u32 pll_sys; /* 0x000 */
u32 pll_sys_set; /* 0x004 */
u32 pll_sys_clr; /* 0x008 */
u32 pll_sys_tog; /* 0x00c */
u32 usb1_pll_480_ctrl; /* 0x010 */
u32 usb1_pll_480_ctrl_set; /* 0x014 */
u32 usb1_pll_480_ctrl_clr; /* 0x018 */
u32 usb1_pll_480_ctrl_tog; /* 0x01c */
u32 usb2_pll_480_ctrl; /* 0x020 */
u32 usb2_pll_480_ctrl_set; /* 0x024 */
u32 usb2_pll_480_ctrl_clr; /* 0x028 */
u32 usb2_pll_480_ctrl_tog; /* 0x02c */
u32 pll_528; /* 0x030 */
u32 pll_528_set; /* 0x034 */
u32 pll_528_clr; /* 0x038 */
u32 pll_528_tog; /* 0x03c */
u32 pll_528_ss; /* 0x040 */
u32 rsvd0[3];
u32 pll_528_num; /* 0x050 */
u32 rsvd1[3];
u32 pll_528_denom; /* 0x060 */
u32 rsvd2[3];
u32 pll_audio; /* 0x070 */
u32 pll_audio_set; /* 0x074 */
u32 pll_audio_clr; /* 0x078 */
u32 pll_audio_tog; /* 0x07c */
u32 pll_audio_num; /* 0x080 */
u32 rsvd3[3];
u32 pll_audio_denom; /* 0x090 */
u32 rsvd4[3];
u32 pll_video; /* 0x0a0 */
u32 pll_video_set; /* 0x0a4 */
u32 pll_video_clr; /* 0x0a8 */
u32 pll_video_tog; /* 0x0ac */
u32 pll_video_num; /* 0x0b0 */
u32 rsvd5[3];
u32 pll_video_denom; /* 0x0c0 */
u32 rsvd6[3];
u32 pll_mlb; /* 0x0d0 */
u32 pll_mlb_set; /* 0x0d4 */
u32 pll_mlb_clr; /* 0x0d8 */
u32 pll_mlb_tog; /* 0x0dc */
u32 pll_enet; /* 0x0e0 */
u32 pll_enet_set; /* 0x0e4 */
u32 pll_enet_clr; /* 0x0e8 */
u32 pll_enet_tog; /* 0x0ec */
u32 pfd_480; /* 0x0f0 */
u32 pfd_480_set; /* 0x0f4 */
u32 pfd_480_clr; /* 0x0f8 */
u32 pfd_480_tog; /* 0x0fc */
u32 pfd_528; /* 0x100 */
u32 pfd_528_set; /* 0x104 */
u32 pfd_528_clr; /* 0x108 */
u32 pfd_528_tog; /* 0x10c */
u32 reg_1p1; /* 0x110 */
u32 reg_1p1_set; /* 0x114 */
u32 reg_1p1_clr; /* 0x118 */
u32 reg_1p1_tog; /* 0x11c */
u32 reg_3p0; /* 0x120 */
u32 reg_3p0_set; /* 0x124 */
u32 reg_3p0_clr; /* 0x128 */
u32 reg_3p0_tog; /* 0x12c */
u32 reg_2p5; /* 0x130 */
u32 reg_2p5_set; /* 0x134 */
u32 reg_2p5_clr; /* 0x138 */
u32 reg_2p5_tog; /* 0x13c */
u32 reg_core; /* 0x140 */
u32 reg_core_set; /* 0x144 */
u32 reg_core_clr; /* 0x148 */
u32 reg_core_tog; /* 0x14c */
u32 ana_misc0; /* 0x150 */
u32 ana_misc0_set; /* 0x154 */
u32 ana_misc0_clr; /* 0x158 */
u32 ana_misc0_tog; /* 0x15c */
u32 ana_misc1; /* 0x160 */
u32 ana_misc1_set; /* 0x164 */
u32 ana_misc1_clr; /* 0x168 */
u32 ana_misc1_tog; /* 0x16c */
u32 ana_misc2; /* 0x170 */
u32 ana_misc2_set; /* 0x174 */
u32 ana_misc2_clr; /* 0x178 */
u32 ana_misc2_tog; /* 0x17c */
u32 tempsense0; /* 0x180 */
u32 tempsense0_set; /* 0x184 */
u32 tempsense0_clr; /* 0x188 */
u32 tempsense0_tog; /* 0x18c */
u32 tempsense1; /* 0x190 */
u32 tempsense1_set; /* 0x194 */
u32 tempsense1_clr; /* 0x198 */
u32 tempsense1_tog; /* 0x19c */
u32 usb1_vbus_detect; /* 0x1a0 */
u32 usb1_vbus_detect_set; /* 0x1a4 */
u32 usb1_vbus_detect_clr; /* 0x1a8 */
u32 usb1_vbus_detect_tog; /* 0x1ac */
u32 usb1_chrg_detect; /* 0x1b0 */
u32 usb1_chrg_detect_set; /* 0x1b4 */
u32 usb1_chrg_detect_clr; /* 0x1b8 */
u32 usb1_chrg_detect_tog; /* 0x1bc */
u32 usb1_vbus_det_stat; /* 0x1c0 */
u32 usb1_vbus_det_stat_set; /* 0x1c4 */
u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
u32 usb1_vbus_det_stat_tog; /* 0x1cc */
u32 usb1_chrg_det_stat; /* 0x1d0 */
u32 usb1_chrg_det_stat_set; /* 0x1d4 */
u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
u32 usb1_chrg_det_stat_tog; /* 0x1dc */
u32 usb1_loopback; /* 0x1e0 */
u32 usb1_loopback_set; /* 0x1e4 */
u32 usb1_loopback_clr; /* 0x1e8 */
u32 usb1_loopback_tog; /* 0x1ec */
u32 usb1_misc; /* 0x1f0 */
u32 usb1_misc_set; /* 0x1f4 */
u32 usb1_misc_clr; /* 0x1f8 */
u32 usb1_misc_tog; /* 0x1fc */
u32 usb2_vbus_detect; /* 0x200 */
u32 usb2_vbus_detect_set; /* 0x204 */
u32 usb2_vbus_detect_clr; /* 0x208 */
u32 usb2_vbus_detect_tog; /* 0x20c */
u32 usb2_chrg_detect; /* 0x210 */
u32 usb2_chrg_detect_set; /* 0x214 */
u32 usb2_chrg_detect_clr; /* 0x218 */
u32 usb2_chrg_detect_tog; /* 0x21c */
u32 usb2_vbus_det_stat; /* 0x220 */
u32 usb2_vbus_det_stat_set; /* 0x224 */
u32 usb2_vbus_det_stat_clr; /* 0x228 */
u32 usb2_vbus_det_stat_tog; /* 0x22c */
u32 usb2_chrg_det_stat; /* 0x230 */
u32 usb2_chrg_det_stat_set; /* 0x234 */
u32 usb2_chrg_det_stat_clr; /* 0x238 */
u32 usb2_chrg_det_stat_tog; /* 0x23c */
u32 usb2_loopback; /* 0x240 */
u32 usb2_loopback_set; /* 0x244 */
u32 usb2_loopback_clr; /* 0x248 */
u32 usb2_loopback_tog; /* 0x24c */
u32 usb2_misc; /* 0x250 */
u32 usb2_misc_set; /* 0x254 */
u32 usb2_misc_clr; /* 0x258 */
u32 usb2_misc_tog; /* 0x25c */
u32 digprog; /* 0x260 */
};