-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathTM4C123GH6PM.h
1830 lines (1650 loc) · 144 KB
/
TM4C123GH6PM.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*****************************************************************************
* Modified from the original as follows:
* - defined TARGET_IS_BLIZZARD_RA1 for compatibility with the TI library
* - in GPIOA_Type struct replaced first __I RESERVED0[255] with
* __IO uint32_t DATA_Bits[255] to access the individual GPIOA bits.
* - added options for the ARMCC v6 compiler (CLANG)
*
* Quantum Leaps on 2018-01-31
* https://www.state-machine.com
*****************************************************************************/
/****************************************************************************************************//**
* @file TM4C123GH6PM.h
*
* @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
* TM4C123GH6PM from Texas Instruments.
*
* @version V12591
* @date 19. February 2014
*
* @note Generated with SVDConv V2.79v
* from CMSIS SVD File 'TM4C123GH6PM.svd.xml' Version 12591,
*
* @par
* Software License Agreement
*
* Texas Instruments (TI) is supplying this software for use solely and
* exclusively on TI's microcontroller products. The software is owned by
* TI and/or its suppliers, and is protected under applicable copyright
* laws. You may not combine this software with "viral" open-source
* software in order to form a larger program.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
* NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
* CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
*
*******************************************************************************************************/
/** @addtogroup Texas Instruments
* @{
*/
/** @addtogroup TM4C123GH6PM
* @{
*/
#ifndef TM4C123GH6PM_H
#define TM4C123GH6PM_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum {
/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* ------------------- TM4C123GH6PM Specific Interrupt Numbers ------------------ */
GPIOA_IRQn = 0, /*!< 0 GPIOA */
GPIOB_IRQn = 1, /*!< 1 GPIOB */
GPIOC_IRQn = 2, /*!< 2 GPIOC */
GPIOD_IRQn = 3, /*!< 3 GPIOD */
GPIOE_IRQn = 4, /*!< 4 GPIOE */
UART0_IRQn = 5, /*!< 5 UART0 */
UART1_IRQn = 6, /*!< 6 UART1 */
SSI0_IRQn = 7, /*!< 7 SSI0 */
I2C0_IRQn = 8, /*!< 8 I2C0 */
PWM0_FAULT_IRQn = 9, /*!< 9 PWM0_FAULT */
PWM0_0_IRQn = 10, /*!< 10 PWM0_0 */
PWM0_1_IRQn = 11, /*!< 11 PWM0_1 */
PWM0_2_IRQn = 12, /*!< 12 PWM0_2 */
QEI0_IRQn = 13, /*!< 13 QEI0 */
ADC0SS0_IRQn = 14, /*!< 14 ADC0SS0 */
ADC0SS1_IRQn = 15, /*!< 15 ADC0SS1 */
ADC0SS2_IRQn = 16, /*!< 16 ADC0SS2 */
ADC0SS3_IRQn = 17, /*!< 17 ADC0SS3 */
WATCHDOG0_IRQn = 18, /*!< 18 WATCHDOG0 */
TIMER0A_IRQn = 19, /*!< 19 TIMER0A */
TIMER0B_IRQn = 20, /*!< 20 TIMER0B */
TIMER1A_IRQn = 21, /*!< 21 TIMER1A */
TIMER1B_IRQn = 22, /*!< 22 TIMER1B */
TIMER2A_IRQn = 23, /*!< 23 TIMER2A */
TIMER2B_IRQn = 24, /*!< 24 TIMER2B */
COMP0_IRQn = 25, /*!< 25 COMP0 */
COMP1_IRQn = 26, /*!< 26 COMP1 */
SYSCTL_IRQn = 28, /*!< 28 SYSCTL */
FLASH_CTRL_IRQn = 29, /*!< 29 FLASH_CTRL */
GPIOF_IRQn = 30, /*!< 30 GPIOF */
UART2_IRQn = 33, /*!< 33 UART2 */
SSI1_IRQn = 34, /*!< 34 SSI1 */
TIMER3A_IRQn = 35, /*!< 35 TIMER3A */
TIMER3B_IRQn = 36, /*!< 36 TIMER3B */
I2C1_IRQn = 37, /*!< 37 I2C1 */
QEI1_IRQn = 38, /*!< 38 QEI1 */
CAN0_IRQn = 39, /*!< 39 CAN0 */
CAN1_IRQn = 40, /*!< 40 CAN1 */
HIB_IRQn = 43, /*!< 43 HIB */
USB0_IRQn = 44, /*!< 44 USB0 */
PWM0_3_IRQn = 45, /*!< 45 PWM0_3 */
UDMA_IRQn = 46, /*!< 46 UDMA */
UDMAERR_IRQn = 47, /*!< 47 UDMAERR */
ADC1SS0_IRQn = 48, /*!< 48 ADC1SS0 */
ADC1SS1_IRQn = 49, /*!< 49 ADC1SS1 */
ADC1SS2_IRQn = 50, /*!< 50 ADC1SS2 */
ADC1SS3_IRQn = 51, /*!< 51 ADC1SS3 */
SSI2_IRQn = 57, /*!< 57 SSI2 */
SSI3_IRQn = 58, /*!< 58 SSI3 */
UART3_IRQn = 59, /*!< 59 UART3 */
UART4_IRQn = 60, /*!< 60 UART4 */
UART5_IRQn = 61, /*!< 61 UART5 */
UART6_IRQn = 62, /*!< 62 UART6 */
UART7_IRQn = 63, /*!< 63 UART7 */
I2C2_IRQn = 68, /*!< 68 I2C2 */
I2C3_IRQn = 69, /*!< 69 I2C3 */
TIMER4A_IRQn = 70, /*!< 70 TIMER4A */
TIMER4B_IRQn = 71, /*!< 71 TIMER4B */
TIMER5A_IRQn = 92, /*!< 92 TIMER5A */
TIMER5B_IRQn = 93, /*!< 93 TIMER5B */
WTIMER0A_IRQn = 94, /*!< 94 WTIMER0A */
WTIMER0B_IRQn = 95, /*!< 95 WTIMER0B */
WTIMER1A_IRQn = 96, /*!< 96 WTIMER1A */
WTIMER1B_IRQn = 97, /*!< 97 WTIMER1B */
WTIMER2A_IRQn = 98, /*!< 98 WTIMER2A */
WTIMER2B_IRQn = 99, /*!< 99 WTIMER2B */
WTIMER3A_IRQn = 100, /*!< 100 WTIMER3A */
WTIMER3B_IRQn = 101, /*!< 101 WTIMER3B */
WTIMER4A_IRQn = 102, /*!< 102 WTIMER4A */
WTIMER4B_IRQn = 103, /*!< 103 WTIMER4B */
WTIMER5A_IRQn = 104, /*!< 104 WTIMER5A */
WTIMER5B_IRQn = 105, /*!< 105 WTIMER5B */
SYSEXC_IRQn = 106, /*!< 106 SYSEXC */
PWM1_0_IRQn = 134, /*!< 134 PWM1_0 */
PWM1_1_IRQn = 135, /*!< 135 PWM1_1 */
PWM1_2_IRQn = 136, /*!< 136 PWM1_2 */
PWM1_3_IRQn = 137, /*!< 137 PWM1_3 */
PWM1_FAULT_IRQn = 138 /*!< 138 PWM1_FAULT */
} IRQn_Type;
/*
* ===========================================================================
* ---------- Interrupt Handler Prototypes -----------------------------------
* ===========================================================================
*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void GPIOPortA_IRQHandler(void);
void GPIOPortB_IRQHandler(void);
void GPIOPortC_IRQHandler(void);
void GPIOPortD_IRQHandler(void);
void GPIOPortE_IRQHandler(void);
void UART0_IRQHandler(void);
void UART1_IRQHandler(void);
void SSI0_IRQHandler(void);
void I2C0_IRQHandler(void);
void PWMFault_IRQHandler(void);
void PWMGen0_IRQHandler(void);
void PWMGen1_IRQHandler(void);
void PWMGen2_IRQHandler(void);
void QEI0_IRQHandler(void);
void ADCSeq0_IRQHandler(void);
void ADCSeq1_IRQHandler(void);
void ADCSeq2_IRQHandler(void);
void ADCSeq3_IRQHandler(void);
void Watchdog_IRQHandler(void);
void Timer0A_IRQHandler(void);
void Timer0B_IRQHandler(void);
void Timer1A_IRQHandler(void);
void Timer1B_IRQHandler(void);
void Timer2A_IRQHandler(void);
void Timer2B_IRQHandler(void);
void Comp0_IRQHandler(void);
void Comp1_IRQHandler(void);
void Comp2_IRQHandler(void);
void SysCtrl_IRQHandler(void);
void FlashCtrl_IRQHandler(void);
void GPIOPortF_IRQHandler(void);
void GPIOPortG_IRQHandler(void);
void GPIOPortH_IRQHandler(void);
void UART2_IRQHandler(void);
void SSI1_IRQHandler(void);
void Timer3A_IRQHandler(void);
void Timer3B_IRQHandler(void);
void I2C1_IRQHandler(void);
void QEI1_IRQHandler(void);
void CAN0_IRQHandler(void);
void CAN1_IRQHandler(void);
void CAN2_IRQHandler(void);
void Hibernate_IRQHandler(void);
void USB0_IRQHandler(void);
void PWMGen3_IRQHandler(void);
void uDMAST_IRQHandler(void);
void uDMAError_IRQHandler(void);
void ADC1Seq0_IRQHandler(void);
void ADC1Seq1_IRQHandler(void);
void ADC1Seq2_IRQHandler(void);
void ADC1Seq3_IRQHandler(void);
void I2S0_IRQHandler(void);
void EBI0_IRQHandler(void);
void GPIOPortJ_IRQHandler(void);
void GPIOPortK_IRQHandler(void);
void GPIOPortL_IRQHandler(void);
void SSI2_IRQHandler(void);
void SSI3_IRQHandler(void);
void UART3_IRQHandler(void);
void UART4_IRQHandler(void);
void UART5_IRQHandler(void);
void UART6_IRQHandler(void);
void UART7_IRQHandler(void);
void I2C2_IRQHandler(void);
void I2C3_IRQHandler(void);
void Timer4A_IRQHandler(void);
void Timer4B_IRQHandler(void);
void Timer5A_IRQHandler(void);
void Timer5B_IRQHandler(void);
void WideTimer0A_IRQHandler(void);
void WideTimer0B_IRQHandler(void);
void WideTimer1A_IRQHandler(void);
void WideTimer1B_IRQHandler(void);
void WideTimer2A_IRQHandler(void);
void WideTimer2B_IRQHandler(void);
void WideTimer3A_IRQHandler(void);
void WideTimer3B_IRQHandler(void);
void WideTimer4A_IRQHandler(void);
void WideTimer4B_IRQHandler(void);
void WideTimer5A_IRQHandler(void);
void WideTimer5B_IRQHandler(void);
void FPU_IRQHandler(void);
void PECI0_IRQHandler(void);
void LPC0_IRQHandler(void);
void I2C4_IRQHandler(void);
void I2C5_IRQHandler(void);
void GPIOPortM_IRQHandler(void);
void GPIOPortN_IRQHandler(void);
void QEI2_IRQHandler(void);
void Fan0_IRQHandler(void);
void GPIOPortP0_IRQHandler(void);
void GPIOPortP1_IRQHandler(void);
void GPIOPortP2_IRQHandler(void);
void GPIOPortP3_IRQHandler(void);
void GPIOPortP4_IRQHandler(void);
void GPIOPortP5_IRQHandler(void);
void GPIOPortP6_IRQHandler(void);
void GPIOPortP7_IRQHandler(void);
void GPIOPortQ0_IRQHandler(void);
void GPIOPortQ1_IRQHandler(void);
void GPIOPortQ2_IRQHandler(void);
void GPIOPortQ3_IRQHandler(void);
void GPIOPortQ4_IRQHandler(void);
void GPIOPortQ5_IRQHandler(void);
void GPIOPortQ6_IRQHandler(void);
void GPIOPortQ7_IRQHandler(void);
void GPIOPortR_IRQHandler(void);
void GPIOPortS_IRQHandler(void);
void PWM1Gen0_IRQHandler(void);
void PWM1Gen1_IRQHandler(void);
void PWM1Gen2_IRQHandler(void);
void PWM1Gen3_IRQHandler(void);
void PWM1Fault_IRQHandler(void);
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
#define __CM4_REV 0x0102 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#define TARGET_IS_BLIZZARD_RA1 1 /*!< Class of device (for TI library) */
/** @} */ /* End of group Configuration_of_CMSIS */
#ifdef __cplusplus
}
#endif
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#include "system_TM4C123GH6PM.h" /*!< TM4C123GH6PM System */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Device_Peripheral_Registers
* @{
*/
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
/* anonymous unions are enabled by default */
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ WATCHDOG0 ================ */
/* ================================================================================ */
/**
* @brief Register map for WATCHDOG0 peripheral (WATCHDOG0)
*/
typedef struct { /*!< WATCHDOG0 Structure */
__IO uint32_t LOAD; /*!< Watchdog Load */
__IO uint32_t VALUE; /*!< Watchdog Value */
__IO uint32_t CTL; /*!< Watchdog Control */
__O uint32_t ICR; /*!< Watchdog Interrupt Clear */
__IO uint32_t RIS; /*!< Watchdog Raw Interrupt Status */
__IO uint32_t MIS; /*!< Watchdog Masked Interrupt Status */
__I uint32_t RESERVED0[256];
__IO uint32_t TEST; /*!< Watchdog Test */
__I uint32_t RESERVED1[505];
__IO uint32_t LOCK; /*!< Watchdog Lock */
} WATCHDOG0_Type;
/* ================================================================================ */
/* ================ GPIOA ================ */
/* ================================================================================ */
/**
* @brief Register map for GPIOA peripheral (GPIOA)
*/
typedef struct { /*!< GPIOA Structure */
__IO uint32_t DATA_Bits[255]; /*!< GPIO bit combinations */
__IO uint32_t DATA; /*!< GPIO Data */
__IO uint32_t DIR; /*!< GPIO Direction */
__IO uint32_t IS; /*!< GPIO Interrupt Sense */
__IO uint32_t IBE; /*!< GPIO Interrupt Both Edges */
__IO uint32_t IEV; /*!< GPIO Interrupt Event */
__IO uint32_t IM; /*!< GPIO Interrupt Mask */
__IO uint32_t RIS; /*!< GPIO Raw Interrupt Status */
__IO uint32_t MIS; /*!< GPIO Masked Interrupt Status */
__O uint32_t ICR; /*!< GPIO Interrupt Clear */
__IO uint32_t AFSEL; /*!< GPIO Alternate Function Select */
__I uint32_t RESERVED1[55];
__IO uint32_t DR2R; /*!< GPIO 2-mA Drive Select */
__IO uint32_t DR4R; /*!< GPIO 4-mA Drive Select */
__IO uint32_t DR8R; /*!< GPIO 8-mA Drive Select */
__IO uint32_t ODR; /*!< GPIO Open Drain Select */
__IO uint32_t PUR; /*!< GPIO Pull-Up Select */
__IO uint32_t PDR; /*!< GPIO Pull-Down Select */
__IO uint32_t SLR; /*!< GPIO Slew Rate Control Select */
__IO uint32_t DEN; /*!< GPIO Digital Enable */
__IO uint32_t LOCK; /*!< GPIO Lock */
__I uint32_t CR; /*!< GPIO Commit */
__IO uint32_t AMSEL; /*!< GPIO Analog Mode Select */
__IO uint32_t PCTL; /*!< GPIO Port Control */
__IO uint32_t ADCCTL; /*!< GPIO ADC Control */
__IO uint32_t DMACTL; /*!< GPIO DMA Control */
} GPIOA_Type;
/* ================================================================================ */
/* ================ SSI0 ================ */
/* ================================================================================ */
/**
* @brief Register map for SSI0 peripheral (SSI0)
*/
typedef struct { /*!< SSI0 Structure */
__IO uint32_t CR0; /*!< SSI Control 0 */
__IO uint32_t CR1; /*!< SSI Control 1 */
__IO uint32_t DR; /*!< SSI Data */
__IO uint32_t SR; /*!< SSI Status */
__IO uint32_t CPSR; /*!< SSI Clock Prescale */
__IO uint32_t IM; /*!< SSI Interrupt Mask */
__IO uint32_t RIS; /*!< SSI Raw Interrupt Status */
__IO uint32_t MIS; /*!< SSI Masked Interrupt Status */
__O uint32_t ICR; /*!< SSI Interrupt Clear */
__IO uint32_t DMACTL; /*!< SSI DMA Control */
__I uint32_t RESERVED0[1000];
__IO uint32_t CC; /*!< SSI Clock Configuration */
} SSI0_Type;
/* ================================================================================ */
/* ================ UART0 ================ */
/* ================================================================================ */
/**
* @brief Register map for UART0 peripheral (UART0)
*/
typedef struct { /*!< UART0 Structure */
__IO uint32_t DR; /*!< UART Data */
union {
__IO uint32_t ECR_UART_ALT; /*!< UART Receive Status/Error Clear */
__IO uint32_t RSR; /*!< UART Receive Status/Error Clear */
};
__I uint32_t RESERVED0[4];
__IO uint32_t FR; /*!< UART Flag */
__I uint32_t RESERVED1;
__IO uint32_t ILPR; /*!< UART IrDA Low-Power Register */
__IO uint32_t IBRD; /*!< UART Integer Baud-Rate Divisor */
__IO uint32_t FBRD; /*!< UART Fractional Baud-Rate Divisor */
__IO uint32_t LCRH; /*!< UART Line Control */
__IO uint32_t CTL; /*!< UART Control */
__IO uint32_t IFLS; /*!< UART Interrupt FIFO Level Select */
__IO uint32_t IM; /*!< UART Interrupt Mask */
__IO uint32_t RIS; /*!< UART Raw Interrupt Status */
__IO uint32_t MIS; /*!< UART Masked Interrupt Status */
__O uint32_t ICR; /*!< UART Interrupt Clear */
__IO uint32_t DMACTL; /*!< UART DMA Control */
__I uint32_t RESERVED2[22];
__IO uint32_t _9BITADDR; /*!< UART 9-Bit Self Address */
__IO uint32_t _9BITAMASK; /*!< UART 9-Bit Self Address Mask */
__I uint32_t RESERVED3[965];
__IO uint32_t PP; /*!< UART Peripheral Properties */
__I uint32_t RESERVED4;
__IO uint32_t CC; /*!< UART Clock Configuration */
} UART0_Type;
/* ================================================================================ */
/* ================ I2C0 ================ */
/* ================================================================================ */
/**
* @brief Register map for I2C0 peripheral (I2C0)
*/
typedef struct { /*!< I2C0 Structure */
__IO uint32_t MSA; /*!< I2C Master Slave Address */
union {
__IO uint32_t MCS_I2C0_ALT; /*!< I2C Master Control/Status */
__IO uint32_t MCS; /*!< I2C Master Control/Status */
};
__IO uint32_t MDR; /*!< I2C Master Data */
__IO uint32_t MTPR; /*!< I2C Master Timer Period */
__IO uint32_t MIMR; /*!< I2C Master Interrupt Mask */
__IO uint32_t MRIS; /*!< I2C Master Raw Interrupt Status */
__IO uint32_t MMIS; /*!< I2C Master Masked Interrupt Status */
__O uint32_t MICR; /*!< I2C Master Interrupt Clear */
__IO uint32_t MCR; /*!< I2C Master Configuration */
__IO uint32_t MCLKOCNT; /*!< I2C Master Clock Low Timeout Count */
__I uint32_t RESERVED0;
__IO uint32_t MBMON; /*!< I2C Master Bus Monitor */
__I uint32_t RESERVED1[2];
__IO uint32_t MCR2; /*!< I2C Master Configuration 2 */
__I uint32_t RESERVED2[497];
__IO uint32_t SOAR; /*!< I2C Slave Own Address */
union {
__IO uint32_t SCSR_I2C0_ALT; /*!< I2C Slave Control/Status */
__IO uint32_t SCSR; /*!< I2C Slave Control/Status */
};
__IO uint32_t SDR; /*!< I2C Slave Data */
__IO uint32_t SIMR; /*!< I2C Slave Interrupt Mask */
__IO uint32_t SRIS; /*!< I2C Slave Raw Interrupt Status */
__IO uint32_t SMIS; /*!< I2C Slave Masked Interrupt Status */
__O uint32_t SICR; /*!< I2C Slave Interrupt Clear */
__IO uint32_t SOAR2; /*!< I2C Slave Own Address 2 */
__IO uint32_t SACKCTL; /*!< I2C Slave ACK Control */
__I uint32_t RESERVED3[487];
__IO uint32_t PP; /*!< I2C Peripheral Properties */
__IO uint32_t PC; /*!< I2C Peripheral Configuration */
} I2C0_Type;
/* ================================================================================ */
/* ================ PWM0 ================ */
/* ================================================================================ */
/**
* @brief Register map for PWM0 peripheral (PWM0)
*/
typedef struct { /*!< PWM0 Structure */
__IO uint32_t CTL; /*!< PWM Master Control */
__IO uint32_t SYNC; /*!< PWM Time Base Sync */
__IO uint32_t ENABLE; /*!< PWM Output Enable */
__IO uint32_t INVERT; /*!< PWM Output Inversion */
__IO uint32_t FAULT; /*!< PWM Output Fault */
__IO uint32_t INTEN; /*!< PWM Interrupt Enable */
__IO uint32_t RIS; /*!< PWM Raw Interrupt Status */
__IO uint32_t ISC; /*!< PWM Interrupt Status and Clear */
__IO uint32_t STATUS; /*!< PWM Status */
__IO uint32_t FAULTVAL; /*!< PWM Fault Condition Value */
__IO uint32_t ENUPD; /*!< PWM Enable Update */
__I uint32_t RESERVED0[5];
__IO uint32_t _0_CTL; /*!< PWM0 Control */
__IO uint32_t _0_INTEN; /*!< PWM0 Interrupt and Trigger Enable */
__IO uint32_t _0_RIS; /*!< PWM0 Raw Interrupt Status */
__IO uint32_t _0_ISC; /*!< PWM0 Interrupt Status and Clear */
__IO uint32_t _0_LOAD; /*!< PWM0 Load */
__IO uint32_t _0_COUNT; /*!< PWM0 Counter */
__IO uint32_t _0_CMPA; /*!< PWM0 Compare A */
__IO uint32_t _0_CMPB; /*!< PWM0 Compare B */
__IO uint32_t _0_GENA; /*!< PWM0 Generator A Control */
__IO uint32_t _0_GENB; /*!< PWM0 Generator B Control */
__IO uint32_t _0_DBCTL; /*!< PWM0 Dead-Band Control */
__IO uint32_t _0_DBRISE; /*!< PWM0 Dead-Band Rising-Edge Delay */
__IO uint32_t _0_DBFALL; /*!< PWM0 Dead-Band Falling-Edge-Delay */
__IO uint32_t _0_FLTSRC0; /*!< PWM0 Fault Source 0 */
__IO uint32_t _0_FLTSRC1; /*!< PWM0 Fault Source 1 */
__IO uint32_t _0_MINFLTPER; /*!< PWM0 Minimum Fault Period */
__IO uint32_t _1_CTL; /*!< PWM1 Control */
__IO uint32_t _1_INTEN; /*!< PWM1 Interrupt and Trigger Enable */
__IO uint32_t _1_RIS; /*!< PWM1 Raw Interrupt Status */
__IO uint32_t _1_ISC; /*!< PWM1 Interrupt Status and Clear */
__IO uint32_t _1_LOAD; /*!< PWM1 Load */
__IO uint32_t _1_COUNT; /*!< PWM1 Counter */
__IO uint32_t _1_CMPA; /*!< PWM1 Compare A */
__IO uint32_t _1_CMPB; /*!< PWM1 Compare B */
__IO uint32_t _1_GENA; /*!< PWM1 Generator A Control */
__IO uint32_t _1_GENB; /*!< PWM1 Generator B Control */
__IO uint32_t _1_DBCTL; /*!< PWM1 Dead-Band Control */
__IO uint32_t _1_DBRISE; /*!< PWM1 Dead-Band Rising-Edge Delay */
__IO uint32_t _1_DBFALL; /*!< PWM1 Dead-Band Falling-Edge-Delay */
__IO uint32_t _1_FLTSRC0; /*!< PWM1 Fault Source 0 */
__IO uint32_t _1_FLTSRC1; /*!< PWM1 Fault Source 1 */
__IO uint32_t _1_MINFLTPER; /*!< PWM1 Minimum Fault Period */
__IO uint32_t _2_CTL; /*!< PWM2 Control */
__IO uint32_t _2_INTEN; /*!< PWM2 Interrupt and Trigger Enable */
__IO uint32_t _2_RIS; /*!< PWM2 Raw Interrupt Status */
__IO uint32_t _2_ISC; /*!< PWM2 Interrupt Status and Clear */
__IO uint32_t _2_LOAD; /*!< PWM2 Load */
__IO uint32_t _2_COUNT; /*!< PWM2 Counter */
__IO uint32_t _2_CMPA; /*!< PWM2 Compare A */
__IO uint32_t _2_CMPB; /*!< PWM2 Compare B */
__IO uint32_t _2_GENA; /*!< PWM2 Generator A Control */
__IO uint32_t _2_GENB; /*!< PWM2 Generator B Control */
__IO uint32_t _2_DBCTL; /*!< PWM2 Dead-Band Control */
__IO uint32_t _2_DBRISE; /*!< PWM2 Dead-Band Rising-Edge Delay */
__IO uint32_t _2_DBFALL; /*!< PWM2 Dead-Band Falling-Edge-Delay */
__IO uint32_t _2_FLTSRC0; /*!< PWM2 Fault Source 0 */
__IO uint32_t _2_FLTSRC1; /*!< PWM2 Fault Source 1 */
__IO uint32_t _2_MINFLTPER; /*!< PWM2 Minimum Fault Period */
__IO uint32_t _3_CTL; /*!< PWM3 Control */
__IO uint32_t _3_INTEN; /*!< PWM3 Interrupt and Trigger Enable */
__IO uint32_t _3_RIS; /*!< PWM3 Raw Interrupt Status */
__IO uint32_t _3_ISC; /*!< PWM3 Interrupt Status and Clear */
__IO uint32_t _3_LOAD; /*!< PWM3 Load */
__IO uint32_t _3_COUNT; /*!< PWM3 Counter */
__IO uint32_t _3_CMPA; /*!< PWM3 Compare A */
__IO uint32_t _3_CMPB; /*!< PWM3 Compare B */
__IO uint32_t _3_GENA; /*!< PWM3 Generator A Control */
__IO uint32_t _3_GENB; /*!< PWM3 Generator B Control */
__IO uint32_t _3_DBCTL; /*!< PWM3 Dead-Band Control */
__IO uint32_t _3_DBRISE; /*!< PWM3 Dead-Band Rising-Edge Delay */
__IO uint32_t _3_DBFALL; /*!< PWM3 Dead-Band Falling-Edge-Delay */
__IO uint32_t _3_FLTSRC0; /*!< PWM3 Fault Source 0 */
__IO uint32_t _3_FLTSRC1; /*!< PWM3 Fault Source 1 */
__IO uint32_t _3_MINFLTPER; /*!< PWM3 Minimum Fault Period */
__I uint32_t RESERVED1[432];
__IO uint32_t _0_FLTSEN; /*!< PWM0 Fault Pin Logic Sense */
__I uint32_t _0_FLTSTAT0; /*!< PWM0 Fault Status 0 */
__I uint32_t _0_FLTSTAT1; /*!< PWM0 Fault Status 1 */
__I uint32_t RESERVED2[29];
__IO uint32_t _1_FLTSEN; /*!< PWM1 Fault Pin Logic Sense */
__I uint32_t _1_FLTSTAT0; /*!< PWM1 Fault Status 0 */
__I uint32_t _1_FLTSTAT1; /*!< PWM1 Fault Status 1 */
__I uint32_t RESERVED3[30];
__I uint32_t _2_FLTSTAT0; /*!< PWM2 Fault Status 0 */
__I uint32_t _2_FLTSTAT1; /*!< PWM2 Fault Status 1 */
__I uint32_t RESERVED4[30];
__I uint32_t _3_FLTSTAT0; /*!< PWM3 Fault Status 0 */
__I uint32_t _3_FLTSTAT1; /*!< PWM3 Fault Status 1 */
__I uint32_t RESERVED5[397];
__IO uint32_t PP; /*!< PWM Peripheral Properties */
} PWM0_Type;
/* ================================================================================ */
/* ================ QEI0 ================ */
/* ================================================================================ */
/**
* @brief Register map for QEI0 peripheral (QEI0)
*/
typedef struct { /*!< QEI0 Structure */
__IO uint32_t CTL; /*!< QEI Control */
__IO uint32_t STAT; /*!< QEI Status */
__IO uint32_t POS; /*!< QEI Position */
__IO uint32_t MAXPOS; /*!< QEI Maximum Position */
__IO uint32_t LOAD; /*!< QEI Timer Load */
__IO uint32_t TIME; /*!< QEI Timer */
__IO uint32_t COUNT; /*!< QEI Velocity Counter */
__IO uint32_t SPEED; /*!< QEI Velocity */
__IO uint32_t INTEN; /*!< QEI Interrupt Enable */
__IO uint32_t RIS; /*!< QEI Raw Interrupt Status */
__IO uint32_t ISC; /*!< QEI Interrupt Status and Clear */
} QEI0_Type;
/* ================================================================================ */
/* ================ TIMER0 ================ */
/* ================================================================================ */
/**
* @brief Register map for TIMER0 peripheral (TIMER0)
*/
typedef struct { /*!< TIMER0 Structure */
__IO uint32_t CFG; /*!< GPTM Configuration */
__IO uint32_t TAMR; /*!< GPTM Timer A Mode */
__IO uint32_t TBMR; /*!< GPTM Timer B Mode */
__IO uint32_t CTL; /*!< GPTM Control */
__IO uint32_t SYNC; /*!< GPTM Synchronize */
__I uint32_t RESERVED0;
__IO uint32_t IMR; /*!< GPTM Interrupt Mask */
__IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */
__IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */
__O uint32_t ICR; /*!< GPTM Interrupt Clear */
__IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */
__IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */
__IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */
__IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */
__IO uint32_t TAPR; /*!< GPTM Timer A Prescale */
__IO uint32_t TBPR; /*!< GPTM Timer B Prescale */
__IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */
__IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */
__IO uint32_t TAR; /*!< GPTM Timer A */
__IO uint32_t TBR; /*!< GPTM Timer B */
__IO uint32_t TAV; /*!< GPTM Timer A Value */
__IO uint32_t TBV; /*!< GPTM Timer B Value */
__IO uint32_t RTCPD; /*!< GPTM RTC Predivide */
__IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */
__IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */
__IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */
__IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */
__I uint32_t RESERVED1[981];
__IO uint32_t PP; /*!< GPTM Peripheral Properties */
} TIMER0_Type;
/* ================================================================================ */
/* ================ WTIMER0 ================ */
/* ================================================================================ */
/**
* @brief Register map for WTIMER0 peripheral (WTIMER0)
*/
typedef struct { /*!< WTIMER0 Structure */
__IO uint32_t CFG; /*!< GPTM Configuration */
__IO uint32_t TAMR; /*!< GPTM Timer A Mode */
__IO uint32_t TBMR; /*!< GPTM Timer B Mode */
__IO uint32_t CTL; /*!< GPTM Control */
__IO uint32_t SYNC; /*!< GPTM Synchronize */
__I uint32_t RESERVED0;
__IO uint32_t IMR; /*!< GPTM Interrupt Mask */
__IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */
__IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */
__O uint32_t ICR; /*!< GPTM Interrupt Clear */
__IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */
__IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */
__IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */
__IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */
__IO uint32_t TAPR; /*!< GPTM Timer A Prescale */
__IO uint32_t TBPR; /*!< GPTM Timer B Prescale */
__IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */
__IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */
__IO uint32_t TAR; /*!< GPTM Timer A */
__IO uint32_t TBR; /*!< GPTM Timer B */
__IO uint32_t TAV; /*!< GPTM Timer A Value */
__IO uint32_t TBV; /*!< GPTM Timer B Value */
__IO uint32_t RTCPD; /*!< GPTM RTC Predivide */
__IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */
__IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */
__IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */
__IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */
__I uint32_t RESERVED1[981];
__IO uint32_t PP; /*!< GPTM Peripheral Properties */
} WTIMER0_Type;
/* ================================================================================ */
/* ================ ADC0 ================ */
/* ================================================================================ */
/**
* @brief Register map for ADC0 peripheral (ADC0)
*/
typedef struct { /*!< ADC0 Structure */
__IO uint32_t ACTSS; /*!< ADC Active Sample Sequencer */
__IO uint32_t RIS; /*!< ADC Raw Interrupt Status */
__IO uint32_t IM; /*!< ADC Interrupt Mask */
__IO uint32_t ISC; /*!< ADC Interrupt Status and Clear */
__IO uint32_t OSTAT; /*!< ADC Overflow Status */
__IO uint32_t EMUX; /*!< ADC Event Multiplexer Select */
__IO uint32_t USTAT; /*!< ADC Underflow Status */
__IO uint32_t TSSEL; /*!< ADC Trigger Source Select */
__IO uint32_t SSPRI; /*!< ADC Sample Sequencer Priority */
__IO uint32_t SPC; /*!< ADC Sample Phase Control */
__IO uint32_t PSSI; /*!< ADC Processor Sample Sequence Initiate */
__I uint32_t RESERVED0;
__IO uint32_t SAC; /*!< ADC Sample Averaging Control */
__IO uint32_t DCISC; /*!< ADC Digital Comparator Interrupt Status and Clear */
__IO uint32_t CTL; /*!< ADC Control */
__I uint32_t RESERVED1;
__IO uint32_t SSMUX0; /*!< ADC Sample Sequence Input Multiplexer Select 0 */
__IO uint32_t SSCTL0; /*!< ADC Sample Sequence Control 0 */
__IO uint32_t SSFIFO0; /*!< ADC Sample Sequence Result FIFO 0 */
__IO uint32_t SSFSTAT0; /*!< ADC Sample Sequence FIFO 0 Status */
__IO uint32_t SSOP0; /*!< ADC Sample Sequence 0 Operation */
__IO uint32_t SSDC0; /*!< ADC Sample Sequence 0 Digital Comparator Select */
__I uint32_t RESERVED2[2];
__IO uint32_t SSMUX1; /*!< ADC Sample Sequence Input Multiplexer Select 1 */
__IO uint32_t SSCTL1; /*!< ADC Sample Sequence Control 1 */
__IO uint32_t SSFIFO1; /*!< ADC Sample Sequence Result FIFO 1 */
__IO uint32_t SSFSTAT1; /*!< ADC Sample Sequence FIFO 1 Status */
__IO uint32_t SSOP1; /*!< ADC Sample Sequence 1 Operation */
__IO uint32_t SSDC1; /*!< ADC Sample Sequence 1 Digital Comparator Select */
__I uint32_t RESERVED3[2];
__IO uint32_t SSMUX2; /*!< ADC Sample Sequence Input Multiplexer Select 2 */
__IO uint32_t SSCTL2; /*!< ADC Sample Sequence Control 2 */
__IO uint32_t SSFIFO2; /*!< ADC Sample Sequence Result FIFO 2 */
__IO uint32_t SSFSTAT2; /*!< ADC Sample Sequence FIFO 2 Status */
__IO uint32_t SSOP2; /*!< ADC Sample Sequence 2 Operation */
__IO uint32_t SSDC2; /*!< ADC Sample Sequence 2 Digital Comparator Select */
__I uint32_t RESERVED4[2];
__IO uint32_t SSMUX3; /*!< ADC Sample Sequence Input Multiplexer Select 3 */
__IO uint32_t SSCTL3; /*!< ADC Sample Sequence Control 3 */
__IO uint32_t SSFIFO3; /*!< ADC Sample Sequence Result FIFO 3 */
__IO uint32_t SSFSTAT3; /*!< ADC Sample Sequence FIFO 3 Status */
__IO uint32_t SSOP3; /*!< ADC Sample Sequence 3 Operation */
__IO uint32_t SSDC3; /*!< ADC Sample Sequence 3 Digital Comparator Select */
__I uint32_t RESERVED5[786];
__O uint32_t DCRIC; /*!< ADC Digital Comparator Reset Initial Conditions */
__I uint32_t RESERVED6[63];
__IO uint32_t DCCTL0; /*!< ADC Digital Comparator Control 0 */
__IO uint32_t DCCTL1; /*!< ADC Digital Comparator Control 1 */
__IO uint32_t DCCTL2; /*!< ADC Digital Comparator Control 2 */
__IO uint32_t DCCTL3; /*!< ADC Digital Comparator Control 3 */
__IO uint32_t DCCTL4; /*!< ADC Digital Comparator Control 4 */
__IO uint32_t DCCTL5; /*!< ADC Digital Comparator Control 5 */
__IO uint32_t DCCTL6; /*!< ADC Digital Comparator Control 6 */
__IO uint32_t DCCTL7; /*!< ADC Digital Comparator Control 7 */
__I uint32_t RESERVED7[8];
__IO uint32_t DCCMP0; /*!< ADC Digital Comparator Range 0 */
__IO uint32_t DCCMP1; /*!< ADC Digital Comparator Range 1 */
__IO uint32_t DCCMP2; /*!< ADC Digital Comparator Range 2 */
__IO uint32_t DCCMP3; /*!< ADC Digital Comparator Range 3 */
__IO uint32_t DCCMP4; /*!< ADC Digital Comparator Range 4 */
__IO uint32_t DCCMP5; /*!< ADC Digital Comparator Range 5 */
__IO uint32_t DCCMP6; /*!< ADC Digital Comparator Range 6 */
__IO uint32_t DCCMP7; /*!< ADC Digital Comparator Range 7 */
__I uint32_t RESERVED8[88];
__IO uint32_t PP; /*!< ADC Peripheral Properties */
__IO uint32_t PC; /*!< ADC Peripheral Configuration */
__IO uint32_t CC; /*!< ADC Clock Configuration */
} ADC0_Type;
/* ================================================================================ */
/* ================ COMP ================ */
/* ================================================================================ */
/**
* @brief Register map for COMP peripheral (COMP)
*/
typedef struct { /*!< COMP Structure */
__IO uint32_t ACMIS; /*!< Analog Comparator Masked Interrupt Status */
__IO uint32_t ACRIS; /*!< Analog Comparator Raw Interrupt Status */
__IO uint32_t ACINTEN; /*!< Analog Comparator Interrupt Enable */
__I uint32_t RESERVED0;
__IO uint32_t ACREFCTL; /*!< Analog Comparator Reference Voltage Control */
__I uint32_t RESERVED1[3];
__IO uint32_t ACSTAT0; /*!< Analog Comparator Status 0 */
__IO uint32_t ACCTL0; /*!< Analog Comparator Control 0 */
__I uint32_t RESERVED2[6];
__IO uint32_t ACSTAT1; /*!< Analog Comparator Status 1 */
__IO uint32_t ACCTL1; /*!< Analog Comparator Control 1 */
__I uint32_t RESERVED3[990];
__IO uint32_t PP; /*!< Analog Comparator Peripheral Properties */
} COMP_Type;
/* ================================================================================ */
/* ================ CAN0 ================ */
/* ================================================================================ */
/**
* @brief Register map for CAN0 peripheral (CAN0)
*/
typedef struct { /*!< CAN0 Structure */
__IO uint32_t CTL; /*!< CAN Control */
__IO uint32_t STS; /*!< CAN Status */
__IO uint32_t ERR; /*!< CAN Error Counter */
__IO uint32_t BIT; /*!< CAN Bit Timing */
__IO uint32_t INT; /*!< CAN Interrupt */
__IO uint32_t TST; /*!< CAN Test */
__IO uint32_t BRPE; /*!< CAN Baud Rate Prescaler Extension */
__I uint32_t RESERVED0;
__IO uint32_t IF1CRQ; /*!< CAN IF1 Command Request */
union {
__IO uint32_t IF1CMSK_CAN0_ALT; /*!< CAN IF1 Command Mask */
__IO uint32_t IF1CMSK; /*!< CAN IF1 Command Mask */
};
__IO uint32_t IF1MSK1; /*!< CAN IF1 Mask 1 */
__IO uint32_t IF1MSK2; /*!< CAN IF1 Mask 2 */
__IO uint32_t IF1ARB1; /*!< CAN IF1 Arbitration 1 */
__IO uint32_t IF1ARB2; /*!< CAN IF1 Arbitration 2 */
__IO uint32_t IF1MCTL; /*!< CAN IF1 Message Control */
__IO uint32_t IF1DA1; /*!< CAN IF1 Data A1 */
__IO uint32_t IF1DA2; /*!< CAN IF1 Data A2 */
__IO uint32_t IF1DB1; /*!< CAN IF1 Data B1 */
__IO uint32_t IF1DB2; /*!< CAN IF1 Data B2 */
__I uint32_t RESERVED1[13];
__IO uint32_t IF2CRQ; /*!< CAN IF2 Command Request */
union {
__IO uint32_t IF2CMSK_CAN0_ALT; /*!< CAN IF2 Command Mask */
__IO uint32_t IF2CMSK; /*!< CAN IF2 Command Mask */
};
__IO uint32_t IF2MSK1; /*!< CAN IF2 Mask 1 */
__IO uint32_t IF2MSK2; /*!< CAN IF2 Mask 2 */
__IO uint32_t IF2ARB1; /*!< CAN IF2 Arbitration 1 */
__IO uint32_t IF2ARB2; /*!< CAN IF2 Arbitration 2 */
__IO uint32_t IF2MCTL; /*!< CAN IF2 Message Control */
__IO uint32_t IF2DA1; /*!< CAN IF2 Data A1 */
__IO uint32_t IF2DA2; /*!< CAN IF2 Data A2 */
__IO uint32_t IF2DB1; /*!< CAN IF2 Data B1 */
__IO uint32_t IF2DB2; /*!< CAN IF2 Data B2 */
__I uint32_t RESERVED2[21];
__IO uint32_t TXRQ1; /*!< CAN Transmission Request 1 */
__IO uint32_t TXRQ2; /*!< CAN Transmission Request 2 */
__I uint32_t RESERVED3[6];
__IO uint32_t NWDA1; /*!< CAN New Data 1 */
__IO uint32_t NWDA2; /*!< CAN New Data 2 */
__I uint32_t RESERVED4[6];
__IO uint32_t MSG1INT; /*!< CAN Message 1 Interrupt Pending */
__IO uint32_t MSG2INT; /*!< CAN Message 2 Interrupt Pending */
__I uint32_t RESERVED5[6];
__IO uint32_t MSG1VAL; /*!< CAN Message 1 Valid */
__IO uint32_t MSG2VAL; /*!< CAN Message 2 Valid */
} CAN0_Type;
/* ================================================================================ */
/* ================ USB0 ================ */
/* ================================================================================ */
/**
* @brief Register map for USB0 peripheral (USB0)
*/
typedef struct { /*!< USB0 Structure */
__IO uint8_t FADDR; /*!< USB Device Functional Address */
__IO uint8_t POWER; /*!< USB Power */
__IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */
__IO uint16_t RXIS; /*!< USB Receive Interrupt Status */
__IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */
__IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */
union {
__IO uint8_t IS_USB0_ALT; /*!< USB General Interrupt Status */
__IO uint8_t IS; /*!< USB General Interrupt Status */
};
union {
__IO uint8_t IE_USB0_ALT; /*!< USB Interrupt Enable */
__IO uint8_t IE; /*!< USB Interrupt Enable */
};
__IO uint16_t FRAME; /*!< USB Frame Value */
__IO uint8_t EPIDX; /*!< USB Endpoint Index */
__IO uint8_t TEST; /*!< USB Test Mode */
__I uint32_t RESERVED0[4];
__IO uint32_t FIFO0; /*!< USB FIFO Endpoint 0 */
__IO uint32_t FIFO1; /*!< USB FIFO Endpoint 1 */
__IO uint32_t FIFO2; /*!< USB FIFO Endpoint 2 */
__IO uint32_t FIFO3; /*!< USB FIFO Endpoint 3 */
__IO uint32_t FIFO4; /*!< USB FIFO Endpoint 4 */
__IO uint32_t FIFO5; /*!< USB FIFO Endpoint 5 */
__IO uint32_t FIFO6; /*!< USB FIFO Endpoint 6 */
__IO uint32_t FIFO7; /*!< USB FIFO Endpoint 7 */
__I uint32_t RESERVED1[8];
__IO uint8_t DEVCTL; /*!< USB Device Control */
__I uint8_t RESERVED2[1];
__IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */
__IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */
__IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */
__IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */
__I uint32_t RESERVED3[4];
__I uint16_t RESERVED4;
__IO uint8_t CONTIM; /*!< USB Connect Timing */
__IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */
__I uint8_t RESERVED5[1];
__IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */
__IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */
__I uint8_t RESERVED6[1];
__IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */
__I uint8_t RESERVED7[1];
__IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */
__IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */
__I uint32_t RESERVED8;
__IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */
__I uint8_t RESERVED9[1];
__IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */
__IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */
__IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */
__I uint8_t RESERVED10[1];
__IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */
__IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */
__IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */
__I uint8_t RESERVED11[1];
__IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */
__IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */
__IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */
__I uint8_t RESERVED12[1];
__IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */
__IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */
__IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */
__I uint8_t RESERVED13[1];
__IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */
__IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */
__IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */
__I uint8_t RESERVED14[1];
__IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */
__IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */
__IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */
__I uint8_t RESERVED15[1];
__IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */
__IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */
__IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */
__I uint8_t RESERVED16[1];
__IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */
__IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */
__IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */
__I uint8_t RESERVED17[1];
__IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */
__IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */
__IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */