Pokemon Crystal is crashing on start

[alloncm]

No description provided.

[alloncm]

Made it boot but still unplayable

Without a bootrom still not booting but not crashing either - stuck at black screen

[alloncm]

Might be connected to the HBlank DMA and the procedures at bank 65 addresses 0x423A and 0x424C

[alloncm]

This the hdma function located at 0x4209:65

                             undefined do_hdma_transfer(u_short source, u_short dest,
             undefined     A:1       <RETURN>
             u_short       HL:2      source
             u_short       DE:2      dest
             byte          C:1       len              Actual len, this method will adapt it to the dma register format
                             do_hdma_transfer                                XREF[2]:     rom65::42ab(c), 
                                                                                          FUN_rom65__42d6:42fc(c)  
     rom65::4209 06 7f           LD         B,0x7f                                           max dma cycles (each cycle copeis 0x10 bytes)
                       Loading src and dst HDMA vars with source and dest parmas
     rom65::420b 7c              LD         A,H
     rom65::420c e0 51           LDH        (offset HDMA1),A                                 = ??
     rom65::420e 7d              LD         A,L
     rom65::420f e6 f0           AND        0xf0
     rom65::4211 e0 52           LDH        (offset HDMA2),A                                 = ??
     rom65::4213 7a              LD         A,D
     rom65::4214 e6 1f           AND        0x1f
     rom65::4216 e0 53           LDH        (offset HDMA3),A                                 = ??
     rom65::4218 7b              LD         A,E
     rom65::4219 e6 f0           AND        0xf0
     rom65::421b e0 54           LDH        (offset HDMA4),A                                 = ??
     rom65::421d 79              LD         A,C
     rom65::421e 0d              DEC        C                                                decrent len param since the amount of dma bytes copied is the (count 
     rom65::421f f6 80           OR         0x80                                             prepare A to be loaded to HDMA5 setting bit 7 to HBlank dma
     rom65::4221 5f              LD         E,A                                              saves A to E which later will be used as HDMA5
                       Wait until LY is smaller than max trasnfer length - len
     rom65::4222 78              LD         A,B
     rom65::4223 91              SUB        C
     rom65::4224 57              LD         D,A
                             initial_wait_loop                               XREF[1]:     rom65::4228(j)  
     rom65::4225 f0 44           LDH        A,(offset LY)                                    = ??
     rom65::4227 ba              CP         D
     rom65::4228 30 fb           JR         NC,initial_wait_loop                             jumps if LY is greater than D
                       Actual DMA transfer start
     rom65::422a f3              DI                                                          We cant be interrupted during transfer
                       Sync to end of Hblank
                             wait_hblank_start_loop                          XREF[1]:     rom65::422f(j)  
     rom65::422b f0 41           LDH        A,(offset STAT)                                  = ??
     rom65::422d e6 03           AND        0x3                                              set A to ppu mode
     rom65::422f 20 fa           JR         NZ,wait_hblank_start_loop                        wait untill hblank starts
                             wait_hblank_end_loop                            XREF[1]:     rom65::4235(j)  
     rom65::4231 f0 41           LDH        A,(offset STAT)                                  read ppu status
     rom65::4233 e6 03           AND        0x3                                              set A to ppu mode
     rom65::4235 28 fa           JR         Z,wait_hblank_end_loop                           wait for hblank mode to end
     rom65::4237 7b              LD         A,E
     rom65::4238 e0 55           LDH        (offset HDMA5),A                                 start DMA transfer with received value
     rom65::423a f0 44           LDH        A,(offset LY)                                    read current scanline 
     rom65::423c 0c              INC        C                                                increase cycles to wait to verify we wait atleast 1 cycle
     rom65::423d 21 44 ff        LD         HL,0xff44                                        set HL with LY reg address
                             wait_transfer_finish_loop                       XREF[2]:     rom65::4241(j), rom65::4245(j)  
     rom65::4240 be              CP         (HL=>LY)                                         compare A (which contains the LY we previously read) with current LY
     rom65::4241 28 fd           JR         Z,wait_transfer_finish_loop                      wait until LY has changed
     rom65::4243 7e              LD         A,(HL=>LY)                                       update LY in A
     rom65::4244 0d              DEC        C                                                decrement counter
     rom65::4245 20 f9           JR         NZ,wait_transfer_finish_loop                     if counter not zero continue the loop
     rom65::4247 21 55 ff        LD         HL,0xff55                                        set HL to HDMA5 reg
     rom65::424a cb be           RES        0x7,(HL=>HDMA5)                                  stop the DMA transfer
     rom65::424c fb              EI                                                          enable interrupts 
     rom65::424d c9              RET
``