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ddr2.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
# Date created = 15:19:42 April 20, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ddr2_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA2F23C8
set_global_assignment -name TOP_LEVEL_ENTITY ddr2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:19:42 APRIL 20, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.0-V LVCMOS"
set_global_assignment -name SDC_FILE project.sdc
###sd card pins
#set_location_assignment PIN_M6 -to GPIO[121]
#set_location_assignment PIN_N9 -to GPIO[123]
#set_location_assignment PIN_P7 -to GPIO[125]
#set_location_assignment PIN_L7 -to GPIO[136]
#set_location_assignment PIN_J7 -to GPIO[140]
#set_location_assignment PIN_H8 -to GPIO[142]
set_location_assignment PIN_M6 -to SD_PIN3
set_location_assignment PIN_N9 -to SD_PIN2
set_location_assignment PIN_P7 -to SD_PIN1
set_location_assignment PIN_L7 -to SD_PIN5
set_location_assignment PIN_J7 -to SD_PIN7
set_location_assignment PIN_H8 -to SD_PIN8
#I don't know why this is needed to compile
set_instance_assignment -name IO_STANDARD "2.5 V" -to SD_PIN5
###
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[10] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[13] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[14] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[15] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[10] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_a[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_ba[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_ba[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_ba[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_cs_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_we_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_ras_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_cas_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_cke -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_odt -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to mem_reset_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[8] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[9] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[10] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[11] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[12] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[13] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[14] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[15] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __ddr3_qsys_uniphy_ddr3_p0
#set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[7] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[8] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[9] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[11] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[12] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[13] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[4] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dq[15] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dqs[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dqs[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dqs_n[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to mem_dqs_n[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|clk[1] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|clk[2] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|clk[3] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|clk[5] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|clk[6] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|p0|umemphy|ureset|phy_reset_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to inst|uniphy_ddr3|p0|umemphy|uread_datapath|read_capture_clk_div2[0] -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to inst|uniphy_ddr3 -tag __ddr3_qsys_uniphy_ddr3_p0
set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to inst|uniphy_ddr3|pll0|upll_memphy|auto_generated|pll1 -tag __ddr3_qsys_uniphy_ddr3_p0
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name UNIPHY_TEMP_VER_CODE 1651952740
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name RAPID_RECOMPILE_MODE ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to da
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to col_le
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to db
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to dc
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to dd
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to de
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to df
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to dg
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to dh
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to le_b
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to le_g
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM" -to le_r
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
#===================================DDR3==================================
#set_location_assignment PIN_M9 -to pll_ref_clk
set_location_assignment PIN_G10 -to pll_ref_clk
set_location_assignment PIN_B11 -to OCT_RZQIN
set_location_assignment PIN_N2 -to global_reset_n
set_location_assignment PIN_G11 -to mem_a[0]
set_location_assignment PIN_G13 -to mem_a[1]
set_location_assignment PIN_H10 -to mem_a[2]
set_location_assignment PIN_D12 -to mem_a[3]
set_location_assignment PIN_A12 -to mem_a[4]
set_location_assignment PIN_C11 -to mem_a[5]
set_location_assignment PIN_B12 -to mem_a[6]
set_location_assignment PIN_H16 -to mem_a[7]
set_location_assignment PIN_L8 -to mem_a[8]
set_location_assignment PIN_H15 -to mem_a[9]
set_location_assignment PIN_E12 -to mem_a[10]
set_location_assignment PIN_H13 -to mem_a[11]
set_location_assignment PIN_J11 -to mem_a[12]
set_location_assignment PIN_D13 -to mem_ba[0]
set_location_assignment PIN_B13 -to mem_ba[1]
set_location_assignment PIN_C13 -to mem_ba[2]
set_location_assignment PIN_J19 -to mem_cas_n
set_location_assignment PIN_A14 -to mem_cke
set_location_assignment PIN_G12 -to mem_ck_n
set_location_assignment PIN_H11 -to mem_ck
set_location_assignment PIN_F12 -to mem_cs_n
set_location_assignment PIN_B16 -to mem_dm[0]
set_location_assignment PIN_K16 -to mem_dm[1]
set_location_assignment PIN_D17 -to mem_dm[2]
set_location_assignment PIN_D17 -to mem_dq[0]
set_location_assignment PIN_C16 -to mem_dq[1]
set_location_assignment PIN_E15 -to mem_dq[2]
set_location_assignment PIN_G17 -to mem_dq[3]
set_location_assignment PIN_F15 -to mem_dq[4]
set_location_assignment PIN_A15 -to mem_dq[5]
set_location_assignment PIN_E16 -to mem_dq[6]
set_location_assignment PIN_G16 -to mem_dq[7]
set_location_assignment PIN_B15 -to mem_dq[8]
set_location_assignment PIN_E14 -to mem_dq[9]
set_location_assignment PIN_C15 -to mem_dq[10]
set_location_assignment PIN_A13 -to mem_dq[11]
set_location_assignment PIN_G15 -to mem_dq[12]
set_location_assignment PIN_F14 -to mem_dq[13]
set_location_assignment PIN_J17 -to mem_dq[14]
set_location_assignment PIN_F13 -to mem_dq[15]
set_location_assignment PIN_H18 -to mem_dqs_n[0]
set_location_assignment PIN_G18 -to mem_dqs[0]
set_location_assignment PIN_J13 -to mem_dqs_n[1]
set_location_assignment PIN_H14 -to mem_dqs[1]
set_location_assignment PIN_K20 -to mem_odt
set_location_assignment PIN_K19 -to mem_ras_n
set_location_assignment PIN_K9 -to mem_reset_n
set_location_assignment PIN_J18 -to mem_we_n
#==========================
#set_location_assignment PIN_U10 -to GPIO[0]
#set_location_assignment PIN_U8 -to GPIO[1]
#set_location_assignment PIN_V9 -to GPIO[2]
#set_location_assignment PIN_V6 -to GPIO[3]
#set_location_assignment PIN_W9 -to GPIO[4]
#set_location_assignment PIN_W8 -to GPIO[5]
#set_location_assignment PIN_T8 -to GPIO[6]
#set_location_assignment PIN_T7 -to GPIO[7]
#set_location_assignment PIN_U7 -to GPIO[8]
#set_location_assignment PIN_U6 -to GPIO[9]
#set_location_assignment PIN_Y9 -to GPIO[10]
#set_location_assignment PIN_Y10 -to GPIO[11]
#set_location_assignment PIN_V10 -to GPIO[12]
#set_location_assignment PIN_Y11 -to GPIO[13]
#set_location_assignment PIN_AB5 -to GPIO[14]
#set_location_assignment PIN_R10 -to GPIO[15]
#set_location_assignment PIN_R11 -to GPIO[16]
#set_location_assignment PIN_U11 -to GPIO[17]
#set_location_assignment PIN_U13 -to GPIO[18]
#set_location_assignment PIN_U12 -to GPIO[19]
#set_location_assignment PIN_Y14 -to GPIO[20]
#set_location_assignment PIN_AB6 -to GPIO[21]
#set_location_assignment PIN_AA8 -to GPIO[22]
#set_location_assignment PIN_AA7 -to GPIO[23]
#set_location_assignment PIN_AB8 -to GPIO[24]
#set_location_assignment PIN_AB7 -to GPIO[25]
#set_location_assignment PIN_AA9 -to GPIO[26]
#set_location_assignment PIN_Y19 -to GPIO[27]
#set_location_assignment PIN_Y3 -to GPIO[28]
#set_location_assignment PIN_Y20 -to GPIO[29]
#set_location_assignment PIN_AB10 -to GPIO[30]
#set_location_assignment PIN_AA10 -to GPIO[31]
#set_location_assignment PIN_AB11 -to GPIO[32]
#set_location_assignment PIN_V13 -to GPIO[33]
#set_location_assignment PIN_AA12 -to GPIO[34]
#set_location_assignment PIN_AB12 -to GPIO[35]
#set_location_assignment PIN_AB13 -to GPIO[36]
#set_location_assignment PIN_R14 -to GPIO[37]
#set_location_assignment PIN_Y15 -to GPIO[38]
#set_location_assignment PIN_AA13 -to GPIO[39]
#set_location_assignment PIN_AB15 -to GPIO[40]
#set_location_assignment PIN_AA14 -to GPIO[41]
#set_location_assignment PIN_AA15 -to GPIO[42]
#set_location_assignment PIN_Y16 -to GPIO[43]
#set_location_assignment PIN_W16 -to GPIO[44]
#set_location_assignment PIN_Y17 -to GPIO[45]
#set_location_assignment PIN_W19 -to GPIO[46]
#set_location_assignment PIN_AB17 -to GPIO[47]
#set_location_assignment PIN_AA17 -to GPIO[48]
#set_location_assignment PIN_AB18 -to GPIO[49]
#set_location_assignment PIN_AA18 -to GPIO[50]
#set_location_assignment PIN_AA19 -to GPIO[51]
#set_location_assignment PIN_AB20 -to GPIO[52]
#set_location_assignment PIN_AA20 -to GPIO[53]
#set_location_assignment PIN_AB21 -to GPIO[54]
#set_location_assignment PIN_AB22 -to GPIO[55]
#set_location_assignment PIN_T9 -to GPIO[56]
#set_location_assignment PIN_T10 -to GPIO[57]
#set_location_assignment PIN_R5 -to GPIO[58]
#set_location_assignment PIN_R6 -to GPIO[59]
#set_location_assignment PIN_R7 -to GPIO[60]
#set_location_assignment PIN_R9 -to GPIO[61]
#set_location_assignment PIN_P8 -to GPIO[62]
#set_location_assignment PIN_P9 -to GPIO[63]
#set_location_assignment PIN_V16 -to GPIO[64]
#set_location_assignment PIN_T14 -to GPIO[65]
#set_location_assignment PIN_Y21 -to GPIO[66]
#set_location_assignment PIN_AA22 -to GPIO[67]
#set_location_assignment PIN_V20 -to GPIO[68]
#set_location_assignment PIN_Y22 -to GPIO[69]
#set_location_assignment PIN_V19 -to GPIO[70]
#set_location_assignment PIN_W21 -to GPIO[71]
#set_location_assignment PIN_W22 -to GPIO[72]
#set_location_assignment PIN_V21 -to GPIO[73]
#set_location_assignment PIN_U21 -to GPIO[74]
#set_location_assignment PIN_V18 -to GPIO[75]
#set_location_assignment PIN_V15 -to GPIO[76]
#set_location_assignment PIN_V14 -to GPIO[77]
#set_location_assignment PIN_U22 -to GPIO[78]
#set_location_assignment PIN_U16 -to GPIO[79]
#set_location_assignment PIN_T22 -to GPIO[80]
#set_location_assignment PIN_T17 -to GPIO[81]
#set_location_assignment PIN_U15 -to GPIO[82]
#set_location_assignment PIN_R21 -to GPIO[83]
#set_location_assignment PIN_R22 -to GPIO[84]
#set_location_assignment PIN_U20 -to GPIO[85]
#set_location_assignment PIN_P22 -to GPIO[86]
#set_location_assignment PIN_N21 -to GPIO[87]
#set_location_assignment PIN_T15 -to GPIO[88]
#set_location_assignment PIN_M21 -to GPIO[89]
#set_location_assignment PIN_R16 -to GPIO[90]
#set_location_assignment PIN_M22 -to GPIO[91]
#set_location_assignment PIN_L22 -to GPIO[92]
#set_location_assignment PIN_R15 -to GPIO[93]
#set_location_assignment PIN_P14 -to GPIO[94]
#set_location_assignment PIN_K22 -to GPIO[95]
#set_location_assignment PIN_K21 -to GPIO[96]
#set_location_assignment PIN_T13 -to GPIO[97]
#set_location_assignment PIN_T12 -to GPIO[98]
#set_location_assignment PIN_R12 -to GPIO[99]
#set_location_assignment PIN_P12 -to GPIO[100]
#set_location_assignment PIN_L18 -to GPIO[101]
#set_location_assignment PIN_U17 -to GPIO[102]
#set_location_assignment PIN_T20 -to GPIO[103]
#set_location_assignment PIN_T19 -to GPIO[104]
#set_location_assignment PIN_T18 -to GPIO[105]
#set_location_assignment PIN_R17 -to GPIO[106]
#set_location_assignment PIN_P16 -to GPIO[107]
#set_location_assignment PIN_P19 -to GPIO[108]
#set_location_assignment PIN_P18 -to GPIO[109]
#set_location_assignment PIN_N20 -to GPIO[110]
#set_location_assignment PIN_N19 -to GPIO[111]
#set_location_assignment PIN_M20 -to GPIO[112]
#set_location_assignment PIN_P17 -to GPIO[113]
#set_location_assignment PIN_N16 -to GPIO[114]
#set_location_assignment PIN_M18 -to GPIO[115]
#set_location_assignment PIN_M16 -to GPIO[116]
#set_location_assignment PIN_L19 -to GPIO[117]
#set_location_assignment PIN_L17 -to GPIO[118]
#set_location_assignment PIN_K17 -to GPIO[119]
#set_location_assignment PIN_M7 -to GPIO[120]
#set_location_assignment PIN_M6 -to GPIO[121]
#set_location_assignment PIN_M8 -to GPIO[122]
#set_location_assignment PIN_N9 -to GPIO[123]
#set_location_assignment PIN_N8 -to GPIO[124]
#set_location_assignment PIN_P7 -to GPIO[125]
#set_location_assignment PIN_N6 -to GPIO[126]
#set_location_assignment PIN_P6 -to GPIO[127]
#set_location_assignment PIN_D6 -to GPIO[128]
#set_location_assignment PIN_E9 -to GPIO[129]
#set_location_assignment PIN_C6 -to GPIO[130]
#set_location_assignment PIN_D7 -to GPIO[131]
#set_location_assignment PIN_C9 -to GPIO[132]
#set_location_assignment PIN_C8 -to GPIO[133]
#set_location_assignment PIN_E10 -to GPIO[134]
#set_location_assignment PIN_F10 -to GPIO[135]
#set_location_assignment PIN_L7 -to GPIO[136]
#set_location_assignment PIN_J9 -to GPIO[137]
#set_location_assignment PIN_K7 -to GPIO[138]
#set_location_assignment PIN_J8 -to GPIO[139]
#set_location_assignment PIN_J7 -to GPIO[140]
#set_location_assignment PIN_H9 -to GPIO[141]
#set_location_assignment PIN_H8 -to GPIO[142]
#set_location_assignment PIN_G10 -to GPIO[143]
#set_location_assignment PIN_F9 -to GPIO[144]
#set_location_assignment PIN_E7 -to GPIO[145]
#set_location_assignment PIN_G8 -to GPIO[146]
#set_location_assignment PIN_F7 -to GPIO[147]
#set_location_assignment PIN_H6 -to GPIO[148]
#set_location_assignment PIN_G6 -to GPIO[149]
#set_location_assignment PIN_D9 -to GPIO[150]
#set_location_assignment PIN_A10 -to GPIO[151]
#set_location_assignment PIN_B10 -to GPIO[152]
#set_location_assignment PIN_A9 -to GPIO[153]
#set_location_assignment PIN_A8 -to GPIO[154]
#set_location_assignment PIN_A7 -to GPIO[155]
#set_location_assignment PIN_B7 -to GPIO[156]
#set_location_assignment PIN_B6 -to GPIO[157]
#set_location_assignment PIN_A5 -to GPIO[158]
#set_location_assignment PIN_B5 -to GPIO[159]
#set_location_assignment PIN_U2 -to GPIO[160]
#set_location_assignment PIN_N1 -to GPIO[161]
#set_location_assignment PIN_L1 -to GPIO[162]
#set_location_assignment PIN_L2 -to GPIO[163]
#set_location_assignment PIN_G2 -to GPIO[164]
#set_location_assignment PIN_G1 -to GPIO[165]
#set_location_assignment PIN_D3 -to GPIO[166]
#set_location_assignment PIN_E2 -to GPIO[167]
set_location_assignment PIN_V5 -to JTAG_TCK
set_location_assignment PIN_W5 -to JTAG_TDI
set_location_assignment PIN_M5 -to JTAG_TDO
set_location_assignment PIN_P5 -to JTAG_TMS
#set_location_assignment PIN_R4 -to NCSO
#set_location_assignment PIN_A1 -to NetFPGA_A1
set_location_assignment PIN_C2 -to USB_UART_RXD
set_location_assignment PIN_C1 -to USB_UART_TXD
set_location_assignment PIN_U1 -to USR_LED[0]
set_location_assignment PIN_W2 -to USR_LED[1]
set_location_assignment PIN_AA1 -to USR_LED[2]
set_location_assignment PIN_AA2 -to USR_LED[3]
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS I" -to OCT_RZQIN
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
#set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to pll_ref_clk
set_global_assignment -name VERILOG_FILE ddr2.v
set_global_assignment -name VERILOG_FILE inital_reset_pulse.v
set_global_assignment -name QIP_FILE kernel/synthesis/kernel.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top