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inamaranth-lang/amaranth (press backspace or delete to remove)There isn t a direct platform override for this anymore after the change to forward it to AsyncFFSynchronizer.
bug
yuyichao
- 1
- Opened 2 hours ago
- #1605
Version: 9167910
If I remove 1 MHz in the example from the documentation,
sim.add_clock(Period(MHz=1))
(from
https://github.com/amaranth-lang/amaranth-lang.github.io/blob/0856ab9702c05600e159de2fc9c4ccbf2dcf3cf6/docs/amaranth/latest/_code/up_counter.py#L71) ...
bug
goekce
- 11
- Opened 17 days ago
- #1603
- RFC PR: https://github.com/eigenform/rfcs/blob/main/text/0074-structured-vcd.md
- Implementation PR: N/A
feature
whitequark
- Opened on May 13
- #1599
- RFC PR: amaranth-lang/rfcs#76
- Documentation PR: N/A
- CI configuration PR: N/A
feature
zyp
- Opened on May 12
- #1595
Amaranth documentation is currently only available under https://amaranth-lang.org/docs/amaranth/ version / for releases
or https://amaranth-lang.org/docs/amaranth/latest/ for HEAD. It would be convenient ...
improvement
- 1
- Opened on May 11
- #1592
Hello, (this is not directly an Amaranth issue, but I think it is worth noting / documenting here)
When generating Verilog code from Amaranth, Vivado fails to recognize read ports with transparency.
...
backend:verilog
bug
toolchain:vivado
upstream
piotro888
- 1
- Opened on May 1
- #1589
Running
from amaranth import *
from amaranth.back.verilog import convert
from amaranth.lib import stream
from amaranth.lib.wiring import In, Component
class A(Component):
a: In(stream.Signature(1, ...
backport:v0.5
bug
rroohhh
- Opened on Apr 14
- #1574
A missing return gives a useful warning:
UserWarning: .elaborate() returned None; missing return statement?
but this is then followed by a cryptic error:
TypeError: Object None is not an Elaboratable ...
improvement
robtaylor
- 4
- Opened on Mar 4
- #1569
Here is my code. May I know why the r_dac_en couldn t assign to output port o_dac_en?
def __init__(self):
super().__init__({
# Output port
o_dac_en : Out(1)
}) ...
question
clin15-logi
- 5
- Opened on Feb 27
- #1566
Adding a clock constraint on a new clock domain called sync causes an error during Jinja template rendering. Taking away
platform.add_clock_constraint(cd_sync.clk, 100e6) or renaming the domain makes the ...
question
qookei
- 3
- Opened on Feb 12
- #1565
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