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Commit dce0a90

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phase1geo
committed
Integrating fix for bug 3054545.
1 parent 3a0448b commit dce0a90

17 files changed

+997
-4
lines changed

‎diags/cdd/exclude15.cdd

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5 18 1fd81 3 4 ffffffff *
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8 /Users/trevorw/projects/covered/diags/verilog 2 -t (main) 2 -vcd (exclude15a.vcd) 2 -y (lib) 2 -o (exclude15a.cdd) 2 -v (exclude15a.v) 2 -D (DUMP) 2 -v (exclude15b.v)
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12 /Users/trevorw/projects/covered/diags/verilog/exclude15a.cdd *
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12 /Users/trevorw/projects/covered/diags/verilog/exclude15b.cdd *
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3 0 $root "$root" 0 NA 0 0 1
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3 0 main "main" 0 exclude15a.v 8 26 1
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1 a 1 10 70005 1 0 0 0 1 17 0 1 0 0 0 0
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1 b 2 10 70008 1 0 0 0 1 17 0 1 0 0 0 0
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1 z 3 11 60005 1 0 0 0 1 17 1 1 0 0 0 0
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3 0 dut_and "main.d" 0 lib/dut_and.v 1 9 1
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2 1 7 7 7 f000f 1 1 100c 0 0 1 1 c
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2 2 7 7 7 b000b 1 1 1004 0 0 1 1 b
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2 3 7 7 7 b000f 1 8 3184 1 2 1 18 0 1 1 1 0 0
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2 4 7 7 7 70007 0 1 1410 0 0 1 1 a
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2 5 7 7 7 7000f 2 35 6 3 4
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1 a 4 3 20008 1 0 0 0 1 17 1 1 0 0 0 0
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1 b 5 4 8 1 0 0 0 1 17 1 1 0 0 0 0
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1 c 6 5 8 1 0 0 0 1 17 1 1 0 0 0 0
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4 5 f 5 5 5
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13 E 3 1282938174 This line is not needed
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3 1 main.u$0 "main.u$0" 0 exclude15a.v 15 24 1

‎diags/cdd/exclude15a.cdd

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5 18 1fd81 3 4 ffffffff *
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8 /Users/trevorw/projects/covered/diags/verilog 2 -t (main) 2 -vcd (exclude15a.vcd) 2 -y (lib) 2 -o (exclude15a.cdd) 2 -v (exclude15a.v) 2 -D (DUMP)
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3 0 $root "$root" 0 NA 0 0 1
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3 0 main "main" 0 exclude15a.v 8 26 1
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1 a 1 10 70005 1 0 0 0 1 17 0 1 0 0 0 0
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1 b 2 10 70008 1 0 0 0 1 17 0 1 0 0 0 0
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1 z 3 11 60005 1 0 0 0 1 17 1 1 0 0 0 0
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3 0 dut_and "main.d" 0 lib/dut_and.v 1 9 1
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2 1 7 7 7 f000f 1 1 1004 0 0 1 1 c
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2 2 7 7 7 b000b 1 1 1004 0 0 1 1 b
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2 3 7 7 7 b000f 1 8 1184 1 2 1 18 0 1 1 1 0 0
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2 4 7 7 7 70007 0 1 1410 0 0 1 1 a
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2 5 7 7 7 7000f 2 35 6 3 4
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1 a 4 3 20008 1 0 0 0 1 17 1 1 0 0 0 0
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1 b 5 4 8 1 0 0 0 1 17 1 1 0 0 0 0
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1 c 6 5 8 1 0 0 0 1 17 1 1 0 0 0 0
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4 5 f 5 5 5
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3 1 main.u$0 "main.u$0" 0 exclude15a.v 15 24 1

‎diags/cdd/exclude15b.cdd

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5 18 1fd81 3 4 ffffffff *
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8 /Users/trevorw/projects/covered/diags/verilog 2 -t (main) 2 -vcd (exclude15b.vcd) 2 -y (lib) 2 -o (exclude15b.cdd) 2 -v (exclude15b.v) 2 -D (DUMP)
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3 0 $root "$root" 0 NA 0 0 1
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3 0 main "main" 0 exclude15b.v 8 26 1
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1 a 1 10 70005 1 0 0 0 1 17 0 1 0 0 0 0
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1 b 2 10 70008 1 0 0 0 1 17 0 1 0 0 0 0
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1 z 3 11 60005 1 0 0 0 1 17 1 1 0 0 0 0
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3 0 dut_and "main.d" 0 lib/dut_and.v 1 9 1
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2 1 7 7 7 f000f 1 1 1008 0 0 1 1 c
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2 2 7 7 7 b000b 1 1 1004 0 0 1 1 b
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2 3 7 7 7 b000f 1 8 1084 1 2 1 18 0 1 1 0 0 0
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2 4 7 7 7 70007 0 1 1410 0 0 1 1 a
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2 5 7 7 7 7000f 2 35 6 3 4
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1 a 4 3 20008 1 0 0 0 1 17 1 1 0 0 0 0
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1 b 5 4 8 1 0 0 0 1 17 1 1 0 0 0 0
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1 c 6 5 8 1 0 0 0 1 17 1 1 0 0 0 0
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4 5 f 5 5 5
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3 1 main.u$0 "main.u$0" 0 exclude15b.v 15 24 1

‎diags/regress/Makefile

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@@ -78,8 +78,8 @@ DIAGS1 = add1 aedge1 aedge1.1 afunc1
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exclude9.8 exclude9.9 exclude10 exclude10.1 exclude10.2 \
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exclude10.3 exclude10.3.1 exclude10.3.2 exclude10.3.3 exclude10.4 \
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exclude10.5 exclude11 exclude12 exclude12.1 exclude12.2 \
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exclude12.3 exclude12.4 exclude12.5 exclude12.6 \
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exclude13 exclude14 expand1 expand2 expand3 \
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exclude12.3 exclude12.4 exclude12.5 exclude12.6 exclude13 \
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exclude14 exclude15 expand1 expand2 expand3 \
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expand4 expand4.1 expand4.2 expand4.3 expand4.4 \
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expand6 expand6.1 expand6.2 expand6.3 exponent1 \
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final1 fdisplay1 finish1 fmonitor1 \

‎diags/regress/exclude15.cfg

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-m E03 exclude15.cdd

‎diags/regress/exclude15.pl

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# Name: exclude15.pl
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# Author: Trevor Williams (phase1geo@gmail.com)
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# Date: 09/18/2008
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# Purpose: Verify a merge followed by an exlusion works properly.
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require "../verilog/regress_subs.pl";
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# Initialize the diagnostic environment
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&initialize( "exclude15", 0, @ARGV );
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# Run both of the CDDs to be merged
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system( "$MAKE DIAG=exclude15a onemergerun" ) && die;
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system( "$MAKE DIAG=exclude15b onemergerun" ) && die;
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# Now perform merge command
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&runMergeCommand( "-o exclude15.cdd exclude15a.cdd exclude15b.cdd" );
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# Create temporary file that will contain an exclusion message
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&runCommand( "echo This line is not needed > exclude15.excl" );
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# Perform exclusion
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&runExcludeCommand( "-f ../regress/exclude15.cfg < exclude15.excl" );
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# Remove temporary exclusion reason file
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system( "rm -f exclude15.excl" ) && die;
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# Generate reports
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&runReportCommand( "-d v -e -x -o exclude15.rptM exclude15.cdd" );
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&runReportCommand( "-d v -e -x -i -o exclude15.rptI exclude15.cdd" );
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# Perform the file comparison checks
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&checkTest( "exclude15", 3, 0 );
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exit 0;
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‎diags/regress/exclude15a.cfg

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-t main -vcd exclude15a.vcd -y lib -o exclude15a.cdd -v exclude15a.v

‎diags/regress/exclude15b.cfg

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-t main -vcd exclude15b.vcd -y lib -o exclude15b.cdd -v exclude15b.v

‎diags/rpt/exclude15.rptI

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::::::::::::::::::::::::::::::::::::::::::::::::::
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:: ::
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:: Covered -- Verilog Coverage Verbose Report ::
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:: ::
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::::::::::::::::::::::::::::::::::::::::::::::::::
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Report generated from CDD file : exclude15.cdd
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* Reported by : Instance
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* Report contains exclusion IDs (value within parenthesis preceding verbose output)
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* Report generated from CDD file that was merged from the following files:
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Filename Leading Hierarchy
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-----------------------------------------------------------------------------------------------------------------
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exclude15a.cdd *
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exclude15b.cdd *
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Instance Hit/ Miss/Total Percent hit
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---------------------------------------------------------------------------------------------------------------------
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$root 0/ 0/ 0 100%
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main 0/ 0/ 0 100%
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main.d 1/ 0/ 1 100%
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---------------------------------------------------------------------------------------------------------------------
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Accumulated 1/ 0/ 1 100%
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---------------------------------------------------------------------------------------------------------------------
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Toggle 0 -> 1 Toggle 1 -> 0
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Instance Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
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---------------------------------------------------------------------------------------------------------------------
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$root 0/ 0/ 0 100% 0/ 0/ 0 100%
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main 0/ 3/ 3 0% 0/ 3/ 3 0%
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main.d 0/ 3/ 3 0% 0/ 3/ 3 0%
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---------------------------------------------------------------------------------------------------------------------
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Accumulated 0/ 6/ 6 0% 0/ 6/ 6 0%
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---------------------------------------------------------------------------------------------------------------------
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Module: main, File: exclude15a.v, Instance: main
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-------------------------------------------------------------------------------------------------------------
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Signals not getting 100% toggle coverage
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EID Signal Toggle
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---------------------------------------------------------------------------------------------------------
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(T01) a 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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(T02) b 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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(T03) z 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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Module: dut_and, File: lib/dut_and.v, Instance: main.d
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-------------------------------------------------------------------------------------------------------------
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Signals not getting 100% toggle coverage
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EID Signal Toggle
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---------------------------------------------------------------------------------------------------------
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(T04) a 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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(T05) b 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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(T06) c 0->1: 1'h0
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......................... 1->0: 1'h0 ...
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Logic Combinations
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Instance Hit/Miss/Total Percent hit
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---------------------------------------------------------------------------------------------------------------------
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$root 0/ 0/ 0 100%
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main 0/ 0/ 0 100%
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main.d 3/ 0/ 3 100%
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---------------------------------------------------------------------------------------------------------------------
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Accumulated 3/ 0/ 3 100%
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---------------------------------------------------------------------------------------------------------------------
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Module: dut_and, File: lib/dut_and.v, Instance: main.d
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-------------------------------------------------------------------------------------------------------------
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Excluded Combinations
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=========================================================================================================
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Line # Expression
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=========================================================================================================
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7: assign a = b & c
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|---1---|
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(E03) Expression 1 (2/3)
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^^^^^^^^^^^^^ - &
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LR | LR | LR
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=0-=|=-0=|=11=
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*
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Reason: This line is not needed
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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State Arc
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Instance Hit/Miss/Total Percent hit Hit/Miss/Total Percent hit
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---------------------------------------------------------------------------------------------------------------------
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$root 0/ 0/ 0 100% 0/ 0/ 0 100%
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main 0/ 0/ 0 100% 0/ 0/ 0 100%
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main.d 0/ 0/ 0 100% 0/ 0/ 0 100%
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---------------------------------------------------------------------------------------------------------------------
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Accumulated 0/ 0/ 0 100% 0/ 0/ 0 100%
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---------------------------------------------------------------------------------------------------------------------
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