CLB.sv

// Generated by CIRCT firtool-1.62.0
module CLB(
  input        clock,
               reset,
  input  [3:0] io_inputs,
  input        io_select,
               io_regEnable,
               io_muxInput,
  output       io_output
);

  reg reg_0;
  always @(posedge clock) begin
    if (reset)
      reg_0 <= 1'h0;
    else if (io_regEnable) begin
      automatic logic [7:0] _GEN = '{1'h1, 1'h0, 1'h0, 1'h1, 1'h0, 1'h1, 1'h1, 1'h0};
      reg_0 <= io_select ? _GEN[io_inputs[2:0]] : io_muxInput;
    end
  end // always @(posedge)
  assign io_output = reg_0;
endmodule